This part of IEC 63093 specifies the dimensions that are of importance for mechanical interchangeability for a preferred range of EP-cores made of ferrite, the essential dimensions of coil formers to be used with them and the locations of their terminal pins on a 2,50 mm printed wiring grid in relation to the base outlines of the cores and the effective parameter values to be used in calculations involving them. It also gives guidelines on allowable limits of surface irregularities applicable to EP-cores.<\/p>\n
The specifications contained in this document are useful in negotiations between ferrite core manufacturers and users about surface irregularities.<\/p>\n
The general considerations upon which the design of this range of cores is based are as given in Annex A.<\/p>\n
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|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 5<\/td>\n | Annex ZA(normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n | ||||||
| 7<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4 Primary dimensions 4.1 General 4.2 Dimensions of EP-cores 4.2.1 Principal dimensions 4.2.2 Effective parameter and Amin values Figures Figure 1 \u2013 Principal dimensions of EP-cores Tables Table 1 \u2013 Principal dimensions of EP-cores <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 4.3 Dimensional limits for coil formers Figure 2 \u2013 Main dimensions of coil formers for EP-cores Table 2 \u2013 Effective parameter and Amin values Table 3 \u2013 Dimensional limits for coil formers for EP-cores <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 4.4 Pin locations and base outlines Figure 3 \u2013 Pin locations (SMD type) viewed from the upper side of the board <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 5 Limits of surface irregularities 5.1 General 5.2 Examples of surface irregularities Figure 4 \u2013 Pin locations (PTH type) viewed from the underside of the board <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 5.3 Chips and ragged edges 5.3.1 General 5.3.2 Chips and ragged edges on the mating surfaces 5.3.3 Chips and ragged edges on the other surfaces Figure 5 \u2013 Examples of surface irregularities <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | Figure 6 \u2013 Chip location for EP-cores <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | Table 4 \u2013 Area and length reference for visual inspection <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 5.4 Cracks 5.5 Flash 5.6 Pull-outs Figure 7 \u2013 Crack and pull-out locations for EP-cores <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 5.7 Crystallites Figure 8 \u2013 Crystallite location for EP-cores Table 5 \u2013 Limits for cracks <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | 5.8 Pores Figure 9 \u2013 Pore location for EP-cores <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | Annex A (normative)EP-core design A.1 General A.2 Pin location and base outlines <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Ferrite cores. Guidelines on dimensions and the limits of surface irregularities – EP-cores and associated parts for use in inductors and transformers<\/b><\/p>\n |