IEC 62433-6:2020 describes the extraction flow for deriving an immunity macro-model of an Integrated Circuit (IC) against conducted Electrostatic Discharge (ESD) according to IEC 61000-4-2 and Electrical Fast Transients (EFT) according to IEC 61000-4-4. The model addresses physical damages due to overvoltage, thermal damage and other failure modes. Functional failures can also be addressed. This model allows the immunity simulation of the IC in an application. This model is commonly called “Integrated Circuit Immunity Model Conducted Pulse Immunity”, ICIM-CPI. This document provides: – the description of ICIM-CPI macro-model elements representing electrical, thermal or logical behaviour of the IC. – a universal data exchange format based on XML.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 5<\/td>\n | Annex ZA(normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 3 Terms, definitions, abbreviated terms and conventions 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 3.2 Abbreviated terms 3.3 Conventions 4 Philosophy <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 5 ICIM-CPI model structure 5.1 General <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | Figures Figure 1 \u2013 Structure of the ICIM-CPI model <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 5.2 PPN 5.2.1 Typical structure of a PPN Figure 2 \u2013 Example of an ICIM-CPI model of an electronic board <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 5.2.2 PDN description Figure 3 \u2013 Structure of a typical PPN <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | 5.2.3 NLB description 5.3 FB description <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | Figure 4 \u2013 Characteristics of a voltage pulse entering the DI during a TLP test <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 6 CPIML format 6.1 General Figure 5 \u2013 Example of defect monitored at the OO when a disturbance is applied to the DI <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | 6.2 CPIML structure Figure 6 \u2013 CPIML inheritance hierarchy <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | 6.3 Global elements 6.4 Header section 6.5 Lead_definitions section Tables Table 1 \u2013 Attributes of Lead tag in the Lead_definitions section <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | 6.6 Macro-models section Table 2 \u2013 Compatibility between the Mode and Type fields for correct CPIML annotation <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | 6.7 Validity section 6.8 PDN 6.9 NLB 6.9.1 General Table 3 \u2013 Definition of the Lead tag for Nlb section <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | 6.9.2 Attribute definitions <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | 6.9.3 Data description Table 4 \u2013 Default values of Unit_voltage and Unit_current Table 5 \u2013 Allowed file extensions for Data_files <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | 6.10 FB 6.10.1 General Figure 7 \u2013 Example of a NLB external file <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | 6.10.2 Attribute definitions Table 6 \u2013 Definition of the Lead tag in Fb section <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | Table 7 \u2013 Table sub-attributes definition Table 8 \u2013 Pulse_characteristics parameters definition <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | Table 9 \u2013 Test_criteria parameters definition <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | 6.10.3 Data description <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | Figure 8 \u2013 Example of an external FB file <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | Annex A (informative) Extraction of model components A.1 General A.2 PPN description A.3 PDN Extraction A.3.1 General A.3.2 S\/Z\/Y-parameter measurement <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | A.3.3 Conventional one-port method A.3.4 Two-port method for low impedance measurement Figure A.1 \u2013 Conventional one-port S-parameters measurement Figure A.2 \u2013 Two-port method for low impedance measurement <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | A.3.5 Two-port method for high impedance measurement A.4 NLB extraction A.4.1 General Figure A.3 \u2013 Two-port method for high impedance measurement <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | A.4.2 TLP test method Figure A.4 \u2013 Example of I\/V measurements to extract NLB <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | Figure A.5 \u2013 TLP method set-up (not powered IC) Figure A.6 \u2013 Example of NLB extraction using standard TLP pulse <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | A.5 FB extraction A.5.1 General A.5.2 Example of FB data in case of test criteria type = Class E_IC <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | Figure A.7 \u2013 Graphs for identification of IC failure mechanism for destruction prediction <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | A.5.3 Example of FB data in case of test criteria type = Class C_IC Table A.1 \u2013 Example of FB data corresponding to Class EIC failure Table A.2 \u2013 Example of FB data corresponding to Class CIC failure <\/td>\n<\/tr>\n | ||||||
| 46<\/td>\n | Annex B (informative) NLB implementation techniques in a circuit simulator B.1 General B.2 NLB modelling based on a R\/I table B.3 NLB modelling based on a switch based model Figure B.1 \u2013 NLB model based on a R\/I table <\/td>\n<\/tr>\n | ||||||
| 47<\/td>\n | B.4 NLB modelling based on physical device model Figure B.2 \u2013 Example of a generic model architecture based on switches for NLB behavioural modelling Figure B.3 \u2013 Example of core MOS large signal model of the GGNMOS <\/td>\n<\/tr>\n | ||||||
| 49<\/td>\n | Annex C (informative) Example of ICIM-CPI model C.1 General C.2 Example of power switch ICIM-CPI model C.2.1 General C.2.2 CPImodel Figure C.1 \u2013 Use of the ICIM-CPI model for simulation <\/td>\n<\/tr>\n | ||||||
| 50<\/td>\n | Figure C.2 \u2013 Power switch V\/I curve for 50 ns-pulse width Figure C.3 \u2013 Power switch ICIM-CPI model Table C.1 \u2013 Synthesis peak voltage and energy for different pulse widths <\/td>\n<\/tr>\n | ||||||
| 52<\/td>\n | C.2.3 ICIM-CPI model use <\/td>\n<\/tr>\n | ||||||
| 53<\/td>\n | Figure C.4 \u2013 Power switch ICIM-CPI model use for ESD protection design Figure C.5 \u2013 Calculated voltage at power switch pin for different ESD protection capacitor values <\/td>\n<\/tr>\n | ||||||
| 54<\/td>\n | C.3 Example of 32-bit microcontroller ICIM-CPI model C.3.1 General Figure C.6 \u2013 Voltage at power switch pin for fog lamp left and right sides Figure C.7 \u2013 Example of 32-bit microcontroller protection devices <\/td>\n<\/tr>\n | ||||||
| 55<\/td>\n | C.3.2 CPImodel <\/td>\n<\/tr>\n | ||||||
| 58<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" EMC IC modelling – Models of integrated circuits for Pulse immunity behavioural simulation. Conducted Pulse Immunity (ICIM-CPI)<\/b><\/p>\n |