IEC 60747-8:2010 gives standards for the following categories of field-effect transistors: – type A: junction-gate type; – type B: insulated-gate depletion (normally on) type; – type C: insulated-gate enhancement (normally off) type. The main changes with respect to the previous edition are listed below. a) “Clause 3 Classification” was moved and added to Clause 1. b) “Clause 4 Terminology and letter symbols” was divided into “Clause 3 Terms and definitions” and “Clause 4 Letter symbols” was amended with additions and deletions. c) Clause 5, 6 and 7 were amended with necessary additions and deletions. This publication is to be read in conjunction with \/2.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 4<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 3 Terms and definitions 3.1 Types of field-effect transistors <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 3.2 General terms <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 3.3 Terms related to ratings and characteristics <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | Figures Figure 1 \u2013 Basic waveforms to specify the gate charges <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | Figure 2 \u2013 Integral times for the turn-on energy Eon and turn-off energy Eoff <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 3.4 Conventional used terms 4 Letter symbols 4.1 General 4.2 Additional general subscripts 4.3 List of letter symbols Tables Table 1 \u2013 Terms for MOSFET in this standard and the conventional used terms for the inverse diode integrated in the MOSFET <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Figure 3 \u2013 Switching times <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | 5 Essential ratings and characteristics 5.1 General 5.2 Ratings (limiting values) <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | 5.3 Characteristics <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | 6 Measuring methods 6.1 General 6.2 Verification of ratings (limiting values) Table 2 \u2013 Acceptance defining characteristics <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | Figure 4 \u2013 Circuit diagram for testing of drain-source voltage Figure 5 \u2013 Circuit diagram for testing of gate-source voltage <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | Figure 6 \u2013 Circuit diagram for testing of gate-drain voltage <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | Figure 7 \u2013 Basic circuit for the testing of drain current <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | Figure 8 \u2013 Circuit diagram for testing of peak drain current Figure 9 \u2013 Basic circuit for the testing of reverse drain current of MOSFETs <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | Figure 10 \u2013 Basic circuit for the testing of peak reverse drain current of MOSFETs <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | Figure 11 \u2013 Circuit diagram for verifying FBSOA <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | Figure 12 \u2013 Circuit diagram for verifying RBSOA Figure 13 \u2013 Test waveforms for verifying RBSOA <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | Figure 14 \u2013 Circuit for testing safe operating pulse duration at load short circuit <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | Figure 15 \u2013 Waveforms of gate-source voltage VGS, drain current ID and voltage VDS during load short circuit condition SCSOA <\/td>\n<\/tr>\n | ||||||
| 46<\/td>\n | Figure 16 \u2013 Circuit for the inductive avalanche switching Figure 17 \u2013 Waveforms of ID, VDS and VGS during unclamped inductive switching <\/td>\n<\/tr>\n | ||||||
| 47<\/td>\n | Figure 18 \u2013 Waveforms of ID, VDS and VGS for the non-repetitive avalanche switching <\/td>\n<\/tr>\n | ||||||
| 48<\/td>\n | 6.3 Methods of measurement Figure 19 \u2013 Circuit diagrams for the measurement drain-source breakdown voltage <\/td>\n<\/tr>\n | ||||||
| 49<\/td>\n | Figure 20 \u2013 Circuit diagram for measurement of gate-source off-statevoltage and gate-source threshold voltage <\/td>\n<\/tr>\n | ||||||
| 50<\/td>\n | Figure 21 \u2013 Circuit diagram for drain leakage (or off-state) current or drain cut-off current measurement <\/td>\n<\/tr>\n | ||||||
| 51<\/td>\n | Figure 22 \u2013 Circuit diagram for measuring of gate cut-off current or gate leakage current <\/td>\n<\/tr>\n | ||||||
| 52<\/td>\n | Figure 23 \u2013 Basic circuit of measurement for on-state resistance Figure 24 \u2013 On-state resistance <\/td>\n<\/tr>\n | ||||||
| 53<\/td>\n | Figure 25 \u2013 Circuit diagram for switching time Figure 26 \u2013 Schematic switching waveforms and times <\/td>\n<\/tr>\n | ||||||
| 54<\/td>\n | Figure 27 \u2013 Circuit for determining the turn-on andturn-off power dissipation and\/or energy <\/td>\n<\/tr>\n | ||||||
| 56<\/td>\n | Figure 28 \u2013 Circuit diagrams for the measurement gate charges <\/td>\n<\/tr>\n | ||||||
| 57<\/td>\n | Figure 29 \u2013 Basic for the measurement of short-circuit input capacitance <\/td>\n<\/tr>\n | ||||||
| 58<\/td>\n | Figure 30 \u2013 Basic circuit for measurement of short-circuit output capacitance (Coss) <\/td>\n<\/tr>\n | ||||||
| 59<\/td>\n | Figure 31 \u2013 Circuit for measurement of reverse transfer capacitance Crss <\/td>\n<\/tr>\n | ||||||
| 60<\/td>\n | Figure 32 \u2013 Circuit for measurement of internal gate resistance <\/td>\n<\/tr>\n | ||||||
| 61<\/td>\n | Figure 33 \u2013 Circuit diagram for MOSFET forward recovery timeand recovered charge (Method 1) Figure 34 \u2013 Current waveform through MOSFET (Method 1) <\/td>\n<\/tr>\n | ||||||
| 62<\/td>\n | Figure 35 \u2013 Circuit diagram for MOSFET forward recovery timeand recovered charge (Method 2) <\/td>\n<\/tr>\n | ||||||
| 63<\/td>\n | Figure 36 \u2013 Current waveform through MOSFET (Method 2) <\/td>\n<\/tr>\n | ||||||
| 64<\/td>\n | Figure 37 \u2013 Circuit diagram for the measurement of drain-source reverse voltage <\/td>\n<\/tr>\n | ||||||
| 65<\/td>\n | Figure 38 \u2013 Basic circuit for the measurement of the output conductance goss (method 1: null method) <\/td>\n<\/tr>\n | ||||||
| 66<\/td>\n | Figure 39 \u2013 Basic circuit for the measurement of the output conductance goss (method 2: two-voltmeter method) <\/td>\n<\/tr>\n | ||||||
| 67<\/td>\n | Figure 40 \u2013 Circuit for the measurement of short-circuitforward transconductance gfs (Method 1: Null method) <\/td>\n<\/tr>\n | ||||||
| 68<\/td>\n | Figure 41 \u2013 Circuit for the measurement of forward transconductance gfs (method 2: two-voltmeter method) <\/td>\n<\/tr>\n | ||||||
| 69<\/td>\n | Figure 42 \u2013 Block diagram for the measurement of equivalent input noise voltage Figure 43 \u2013 Circuit for the measurement of equivalent input noise voltage <\/td>\n<\/tr>\n | ||||||
| 70<\/td>\n | Figure 44 \u2013 Circuit diagram for the measurement of on-state drain-source resistance <\/td>\n<\/tr>\n | ||||||
| 71<\/td>\n | Figure 45 \u2013 Circuit diagram <\/td>\n<\/tr>\n | ||||||
| 73<\/td>\n | 7 Acceptance and reliability 7.1 General requirements 7.2 Acceptance-defining characteristics Table 3 \u2013 Acceptance-defining characteristics for endurance and reliability tests <\/td>\n<\/tr>\n | ||||||
| 74<\/td>\n | 7.3 Endurance and reliability tests Figure 46 \u2013 Circuit for high-temperature blockings Figure 47 \u2013 Circuit for high-temperature gate bias <\/td>\n<\/tr>\n | ||||||
| 75<\/td>\n | 7.4 Type tests and routine tests Figure 48 \u2013 Circuit for intermittent operating life <\/td>\n<\/tr>\n | ||||||
| 76<\/td>\n | Table 4 \u2013 Minimum type and routine tests for FETs when applicable <\/td>\n<\/tr>\n | ||||||
| 77<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Semiconductor devices. Discrete devices – Field-effect transistors<\/b><\/p>\n |