{"id":79410,"date":"2024-10-17T18:34:09","date_gmt":"2024-10-17T18:34:09","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-896-10-1997\/"},"modified":"2024-10-24T19:40:02","modified_gmt":"2024-10-24T19:40:02","slug":"ieee-896-10-1997","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-896-10-1997\/","title":{"rendered":"IEEE 896.10 1997"},"content":{"rendered":"
New IEEE Standard – Inactive – Withdrawn. In the Futurebus+ series of standards, tools with which high-performance bus-based systems may be developed are provided. This architecture provides a wide range of performance scalability over both cost and time for multiple generations of single- and multiple-bus multiprocessor systems. This document, a companion standard to the ISO\/IEC 10857: 1994 (ANSI\/IEEE Std 896.1, 1994 Edition) Futurebus+(R) Logical Layer Specification, builds on the logical layer by adding requirements for a spaceborne profile. It is to this profile that products will claim conformance. Other specifications may be required in conjunction with this standard.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | Title Page <\/td>\n<\/tr>\n | ||||||
3<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 1. Overview 1.1 Scope 1.2 Applicability 1.3 Background to the standard <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1.4 Structure of the standard 1.5 How to use this standard <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 1.6 Why use this standard <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 2. References 2.1 Referenced documents <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 2.2 Conflicting standards <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 3. Definitions 3.1 Special word usage 3.2 Bus line and signal conditions <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 3.3 Futurebus+ terminology <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 3.4 Conventions 3.5 Syntax <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 3.6 Futurebus+ logo <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 4. Profile S reference specification 4.1 Introduction <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 4.2 Target applications 4.3 Reference tables <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 4.4 Profile S interoperability <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 4.5 Conformance testing <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 5. Detailed specification, Futurebus+ logical layer 5.1 Arbitration 5.2 Parallel protocol <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 6. Utility Signals 6.1 Trigger 0 (TR0*) and Trigger 1 (TR1*) 6.2 Run (RUN*) 6.3 Nuclear Event Detect (NED*) <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | 6.4 Power Failure Imminent (PFI*) <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 6.5 Power Normal (PN) 6.6 System Reset (SR*) 6.7 Utility Spares (UPSP* and UWSP) <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 7. Fault tolerance aspects of the parallel protocol and utility signals 7.1 Error detection <\/td>\n<\/tr>\n | ||||||
45<\/td>\n | 7.2 Error isolation, logging, and diagnostics <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 7.3 Error removal and recovery <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 7.4 Pinout summary <\/td>\n<\/tr>\n | ||||||
54<\/td>\n | 8. Serial Bus 8.1 Serial Bus physical layer <\/td>\n<\/tr>\n | ||||||
55<\/td>\n | 8.2 Serial Bus link layer 8.3 Serial Bus transaction layer <\/td>\n<\/tr>\n | ||||||
57<\/td>\n | 9. Bus\/Node management and CSRs 9.1 Addressing 9.2 Byte-Lane wiring and byte ordering 9.3 CSRs <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 9.4 Futurebus+ CSRs <\/td>\n<\/tr>\n | ||||||
90<\/td>\n | 9.5 Unit space CSRs <\/td>\n<\/tr>\n | ||||||
98<\/td>\n | 9.6 Serial Bus management <\/td>\n<\/tr>\n | ||||||
99<\/td>\n | 9.7 Private space <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | 9.8 Interrupts 9.9 Diagnostics and test 9.10 Monarch selection <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | 10. Detailed specification, physical layer\u2014SEM-E Stretch 10.1 Mechanical 10.2 Input\/Output 10.3 Profile connector, power, and signal pin assignments <\/td>\n<\/tr>\n | ||||||
131<\/td>\n | 11. Detailed specification, Physical layer\u201410 SU 11.1 Mechanical 11.2 Input\/Output 11.3 Profile connector, power, and signal pin assignments <\/td>\n<\/tr>\n | ||||||
168<\/td>\n | 12. Profile S electrical 12.1 Backplane characteristics and design requirements <\/td>\n<\/tr>\n | ||||||
169<\/td>\n | 12.2 Module electrical characteristics and design requirements <\/td>\n<\/tr>\n | ||||||
175<\/td>\n | 13. Profile S power 13.1 Module power <\/td>\n<\/tr>\n | ||||||
176<\/td>\n | 13.2 Host system power supplies <\/td>\n<\/tr>\n | ||||||
179<\/td>\n | 14. Profile S environmental specifications 14.1 System environmental requirements 14.2 Module environmental requirements <\/td>\n<\/tr>\n | ||||||
180<\/td>\n | 15. Recommended practices 15.1 Thermal considerations 15.2 Power consumption <\/td>\n<\/tr>\n | ||||||
181<\/td>\n | 15.3 Pinouts 15.4 Bus performance analysis <\/td>\n<\/tr>\n | ||||||
182<\/td>\n | 15.5 Bandwidth considerations <\/td>\n<\/tr>\n | ||||||
185<\/td>\n | 16. Profile S module selection criteria 16.1 Introduction 16.2 Profile S modules <\/td>\n<\/tr>\n | ||||||
186<\/td>\n | 16.3 Profile S systems <\/td>\n<\/tr>\n | ||||||
187<\/td>\n | 17. Alternate profile S module connector 17.1 Mechanical 17.2 Input\/Output 17.3 Profile connector, power, and signal pin assignments <\/td>\n<\/tr>\n | ||||||
217<\/td>\n | Annex A\u2014Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Standard for Futurebus+(R) Spaceborne Systems – Profile S<\/b><\/p>\n |