{"id":415001,"date":"2024-10-20T06:02:56","date_gmt":"2024-10-20T06:02:56","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-8802-32021-amd-13-2022\/"},"modified":"2024-10-26T11:16:17","modified_gmt":"2024-10-26T11:16:17","slug":"ieee-8802-32021-amd-13-2022","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-8802-32021-amd-13-2022\/","title":{"rendered":"IEEE 8802-3:2021\/Amd 13-2022"},"content":{"rendered":"

Adoption Standard – Active. This amendment includes changes to IEEE Std 802.3-2018 and adds Clause 152 through Clause 154 and Annex 154A. This amendment adds 100 Gb\/s Physical Layer specifications and management parameters for operation over DWDM systems using a combination of phase and amplitude modulation with coherent detection for reaches of at least 80 km.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
4<\/td>\nBlank Page <\/td>\n<\/tr>\n
5<\/td>\nTitle page <\/td>\n<\/tr>\n
7<\/td>\nImportant Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n
10<\/td>\nParticipants <\/td>\n<\/tr>\n
13<\/td>\nIntroduction <\/td>\n<\/tr>\n
17<\/td>\nContents <\/td>\n<\/tr>\n
25<\/td>\n1. Introduction
1.3 Normative references
1.4 Definitions <\/td>\n<\/tr>\n
26<\/td>\n1.5 Abbreviations <\/td>\n<\/tr>\n
27<\/td>\n30. Management
30.2 Managed Objects
30.2.5 Capabilities
30.5 Layer management for medium attachment units (MAUs)
30.5.1 MAU managed object class
30.5.1.1 MAU attributes
30.5.1.1.2 aMAUType <\/td>\n<\/tr>\n
28<\/td>\n30.5.1.1.15 aFECAbility
30.5.1.1.16 aFECmode
30.5.1.1.17 aFECCorrectedBlocks <\/td>\n<\/tr>\n
29<\/td>\n30.5.1.1.18 aFECUncorrectableBlocks
30.5.1.1.26 aRSFECBIPErrorCount <\/td>\n<\/tr>\n
30<\/td>\n30.5.1.1.27 aRSFECLaneMapping
30.5.1.1.27a aSCFECLaneMapping
30.5.1.1.28 aRSFECBypassAbility <\/td>\n<\/tr>\n
31<\/td>\n30.5.1.1.29 aRSFECBypassIndicationAbility
30.5.1.1.32 aPCSFECBypassIndicationAbility <\/td>\n<\/tr>\n
32<\/td>\n45. Management Data Input\/Output (MDIO) Interface
45.2 MDIO Interface Registers
45.2.1 PMA\/PMD registers <\/td>\n<\/tr>\n
33<\/td>\n45.2.1.6 PMA\/PMD control 2 register (Register 1.7)
45.2.1.7 PMA\/PMD status 2 register (Register 1.8)
45.2.1.7.4 Transmit fault (1.8.11) <\/td>\n<\/tr>\n
34<\/td>\n45.2.1.7.5 Receive fault (1.8.10)
45.2.1.8 PMD transmit disable register (Register 1.9)
45.2.1.21b 40G\/100G PMA\/PMD extended ability 2 register (Register 1.26) <\/td>\n<\/tr>\n
35<\/td>\n45.2.1.21b.3aa 100GBASE-ZR ability (1.26.6)
45.2.1.133a Tx optical channel control register (Register 1.800)
45.2.1.133a.1 Tx optical channel index (1.800.5:0)
45.2.1.133b Tx optical channel ability 1 register (Register 1.801) <\/td>\n<\/tr>\n
36<\/td>\n45.2.1.133b.1 Tx index ability 0 through 15 (1.801.0 through 1.801.15)
45.2.1.133c Tx optical channel ability 2 register (Register 1.802) <\/td>\n<\/tr>\n
37<\/td>\n45.2.1.133c.1 Tx index ability 16 through 31 (1.802.0 through 1.802.15) <\/td>\n<\/tr>\n
38<\/td>\n45.2.1.133d Tx optical channel ability 3 register (Register 1.803)
45.2.1.133d.1 Tx index ability 32 through 47 (1.803.0 through 1.803.15) <\/td>\n<\/tr>\n
39<\/td>\n45.2.1.133e Rx optical channel control register (Register 1.820)
45.2.1.133e.1 Tx Rx different optical channel ability (1.820.15)
45.2.1.133e.2 Rx optical channel index (1.820.5:0) <\/td>\n<\/tr>\n
40<\/td>\n45.2.1.133f Rx optical channel ability 1 register (Register 1.821)
45.2.1.133f.1 Rx index ability 0 through 15 (1.821.0 through 1.821.15) <\/td>\n<\/tr>\n
41<\/td>\n45.2.1.133g Rx optical channel ability 2 register (Register 1.822) <\/td>\n<\/tr>\n
42<\/td>\n45.2.1.133g.1 Rx index ability 16 through 31 (1.822.0 through 1.822.15)
45.2.1.133h Rx optical channel ability 3 register (Register 1.823) <\/td>\n<\/tr>\n
43<\/td>\n45.2.1.133h.1 Rx index ability 32 through 47 (1.823.0 through 1.823.15)
45.2.1.186aa IFEC control register (Register 1.2200)
45.2.1.186aa.1 IFEC bypass indication enable (1.2200.1)
45.2.1.186aa.2 IFEC bypass correction enable (1.2200.0)
45.2.1.186ab IFEC status register (Register 1.2201) <\/td>\n<\/tr>\n
44<\/td>\n45.2.1.186ab.1 PCS align status (1.2201.15)
45.2.1.186ab.2 IFEC align status (1.2201.14)
45.2.1.186ab.3 IFEC AM lock 3 (1.2201.11) <\/td>\n<\/tr>\n
45<\/td>\n45.2.1.186ab.4 IFEC AM lock 2 (1.2201.10)
45.2.1.186ab.5 IFEC AM lock 1 (1.2201.9)
45.2.1.186ab.6 IFEC AM lock 0 (1.2201.8)
45.2.1.186ab.7 IFEC high SER (1.2201.2)
45.2.1.186ab.8 IFEC bypass indication ability (1.2201.1)
45.2.1.186ab.9 IFEC bypass correction ability (1.2201.0)
45.2.1.186ac IFEC corrected codewords counter (Register 1.2202, 1.2203) <\/td>\n<\/tr>\n
46<\/td>\n45.2.1.186ad IFEC uncorrected codewords counter (Register 1.2204, 1.2205)
45.2.1.186ae IFEC lane mapping register (Register 1.2206) <\/td>\n<\/tr>\n
47<\/td>\n45.2.1.186af IFEC symbol error counter, lane 0 (Register 1.2210, 1.2211)
45.2.1.186ag IFEC symbol error counter, lane 1 through 3 (Register 1.2212, 1.2213, 1.2214, 1.2215, 1.2216, 1.2217)
45.2.1.186ah SC-FEC alignment status 1 register (Register 1.2246)
45.2.1.186ah.1 SC-FEC align status (1.2246.12) <\/td>\n<\/tr>\n
48<\/td>\n45.2.1.186ah.2 SC-FEC FAS lock 7 (1.2246.7)
45.2.1.186ah.3 SC-FEC FAS lock 6 (1.2246.6)
45.2.1.186ah.4 SC-FEC FAS lock 5 (1.2246.5) <\/td>\n<\/tr>\n
49<\/td>\n45.2.1.186ah.5 SC-FEC FAS lock 4 (1.2246.4)
45.2.1.186ah.6 SC-FEC FAS lock 3 (1.2246.3)
45.2.1.186ah.7 SC-FEC FAS lock 2 (1.2246.2)
45.2.1.186ah.8 SC-FEC FAS lock 1 (1.2246.1)
45.2.1.186ah.9 SC-FEC FAS lock 0 (1.2246.0)
45.2.1.186ai SC-FEC alignment status 2 register (Register 1.2247) <\/td>\n<\/tr>\n
50<\/td>\n45.2.1.186ai.1 SC-FEC FAS lock 19 (1.2247.11)
45.2.1.186ai.2 SC-FEC FAS lock 18 (1.2247.10)
45.2.1.186ai.3 SC-FEC FAS lock 17 (1.2247.9) <\/td>\n<\/tr>\n
51<\/td>\n45.2.1.186ai.4 SC-FEC FAS lock 16 (1.2247.8)
45.2.1.186ai.5 SC-FEC FAS lock 15 (1.2247.7)
45.2.1.186ai.6 SC-FEC FAS lock 14 (1.2247.6)
45.2.1.186ai.7 SC-FEC FAS lock 13 (1.2247.5)
45.2.1.186ai.8 SC-FEC FAS lock 12 (1.2247.4)
45.2.1.186ai.9 SC-FEC FAS lock 11 (1.2247.3)
45.2.1.186ai.10 SC-FEC FAS lock 10 (1.2247.2)
45.2.1.186ai.11 SC-FEC FAS lock 9 (1.2247.1) <\/td>\n<\/tr>\n
52<\/td>\n45.2.1.186ai.12 SC-FEC FAS lock 8 (1.2247.0)
45.2.1.186aj SC-FEC lane mapping, lane 0 register (Register 1.2250)
45.2.1.186ak SC-FEC lane mapping, lane 1 through 19 registers (Registers 1.2251 through 1.2269)
45.2.1.186al SC-FEC corrected codewords counter (Register 1.2276, 1.2277) <\/td>\n<\/tr>\n
53<\/td>\n45.2.1.186am SC-FEC uncorrected codewords counter (Register 1.2278, 1.2279)
45.2.1.186an SC-FEC total bits register (Register 1.2280, 1.2281, 1.2282, 1.2283)
45.2.1.186ao SC-FEC corrected bits register (Register 1.2284, 1.2285, 1.2286, 1.2287) <\/td>\n<\/tr>\n
55<\/td>\n78. Energy-Efficient Ethernet (EEE)
78.1 Overview
78.1.4 PHY types optionally supporting EEE <\/td>\n<\/tr>\n
56<\/td>\n80. Introduction to 40 Gb\/s and 100 Gb\/s networks
80.1 Overview
80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model
80.1.4 Nomenclature <\/td>\n<\/tr>\n
57<\/td>\n80.1.5 Physical Layer signaling systems
80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers
80.2.2 Physical Coding Sublayer (PCS) <\/td>\n<\/tr>\n
58<\/td>\n80.2.3 Forward Error Correction (FEC) sublayers
80.2.4 Physical Medium Attachment (PMA) sublayer
80.2.5 Physical Medium Dependent (PMD) sublayer
80.3 Service interface specification method and notation
80.3.2 Instances of the Inter-sublayer service interface <\/td>\n<\/tr>\n
60<\/td>\n80.4 Delay constraints
80.5 Skew constraints <\/td>\n<\/tr>\n
61<\/td>\n80.7 Protocol implementation conformance statement (PICS) proforma <\/td>\n<\/tr>\n
62<\/td>\n82. Physical Coding Sublayer (PCS) for 64B\/66B, type 40GBASE-R and 100GBASE-R
82.2 Physical Coding Sublayer (PCS)
82.2.3 64B\/66B transmission code
82.2.3.3 Block structure <\/td>\n<\/tr>\n
63<\/td>\n152. Inverse RS-FEC sublayer
152.1 Overview
152.1.1 Scope
152.1.2 Position of Inverse RS-FEC in the 100GBASE-R sublayers
152.2 Inverse RS-FEC service interface
152.3 PMA or FEC sublayer compatibility
152.4 Delay constraints <\/td>\n<\/tr>\n
64<\/td>\n152.5 Functions within the Inverse RS-FEC sublayer
152.5.1 Functional block diagram <\/td>\n<\/tr>\n
65<\/td>\n152.5.2 Transmit function
152.5.2.1 Alignment lock and deskew <\/td>\n<\/tr>\n
66<\/td>\n152.5.2.2 Lane reorder
152.5.2.3 Reed-Solomon decoder
152.5.2.4 Alignment marker removal
152.5.2.5 256B\/257B to 64B\/66B transcoder <\/td>\n<\/tr>\n
67<\/td>\n152.5.2.6 Block distribution
152.5.2.7 Alignment marker mapping and insertion <\/td>\n<\/tr>\n
68<\/td>\n152.5.2.8 Transmit bit ordering <\/td>\n<\/tr>\n
70<\/td>\n152.5.3 Receive function
152.5.3.1 Lane block synchronization
152.5.3.2 Alignment lock and deskew
152.5.3.3 Lane reorder
152.5.3.4 Alignment marker removal
152.5.3.5 64B\/66B to 256B\/257B transcoder <\/td>\n<\/tr>\n
71<\/td>\n152.5.3.6 Alignment marker mapping and insertion <\/td>\n<\/tr>\n
73<\/td>\n152.5.3.7 Reed-Solomon encoder
152.5.3.8 Symbol distribution
152.5.3.9 Receive bit ordering <\/td>\n<\/tr>\n
75<\/td>\n152.5.4 Detailed functions and state diagrams
152.5.4.1 State diagram conventions
152.5.4.2 State variables
152.5.4.2.1 Variables <\/td>\n<\/tr>\n
76<\/td>\n152.5.4.2.2 Functions <\/td>\n<\/tr>\n
77<\/td>\n152.5.4.2.3 Counters
152.5.4.3 State diagrams
152.6 Inverse RS-FEC MDIO function mapping
152.6.1 IFEC_bypass_correction_enable <\/td>\n<\/tr>\n
78<\/td>\n152.6.2 IFEC_bypass_indication_enable
152.6.3 IFEC_bypass_correction_ability <\/td>\n<\/tr>\n
79<\/td>\n152.6.4 IFEC_bypass_indication_ability
152.6.5 hi_ser
152.6.6 amps_lock
152.6.7 IFEC_align_status
152.6.8 IFEC_corrected_cw_counter
152.6.9 IFEC_uncorrected_cw_counter
152.6.10 IFEC_lane_mapping <\/td>\n<\/tr>\n
80<\/td>\n152.6.11 IFEC_symbol_error_counter_i
152.6.12 align_status
152.6.13 BIP_error_counter_i
152.6.14 lane_mapping
152.6.15 block_lock
152.6.16 am_lock <\/td>\n<\/tr>\n
81<\/td>\n152.7 Protocol implementation conformance statement (PICS) proforma for Clause 152, Inverse RS-FEC sublayer
152.7.1 Introduction
152.7.2 Identification
152.7.2.1 Implementation identification
152.7.2.2 Protocol summary <\/td>\n<\/tr>\n
82<\/td>\n152.7.3 Major capabilities\/options
152.7.4 PICS proforma tables for Inverse RS-FEC sublayer
152.7.4.1 Transmit function <\/td>\n<\/tr>\n
83<\/td>\n152.7.4.2 Receive Function <\/td>\n<\/tr>\n
84<\/td>\n152.7.4.3 State diagrams <\/td>\n<\/tr>\n
85<\/td>\n153. SC-FEC and 100GBASE-ZR Physical Medium Attachment (PMA) sublayer for 100GBASE-ZR PHYs
153.1 Overview
153.1.1 Scope
153.1.2 Position of SC-FEC and 100GBASE-ZR PMA in the 100GBASE-R sublayers
153.2 SC-FEC sublayer
153.2.1 FEC service interface <\/td>\n<\/tr>\n
86<\/td>\n153.2.2 Delay constraints <\/td>\n<\/tr>\n
87<\/td>\n153.2.3 Functions within the SC-FEC sublayer
153.2.3.1 Functional block diagram
153.2.3.2 Transmit function
153.2.3.2.1 Lane block synchronization <\/td>\n<\/tr>\n
88<\/td>\n153.2.3.2.2 Alignment lock and deskew
153.2.3.2.3 Lane reorder
153.2.3.2.4 GMP mapper <\/td>\n<\/tr>\n
91<\/td>\n153.2.3.2.5 SC-FEC encoder
153.2.3.2.6 Scrambler <\/td>\n<\/tr>\n
92<\/td>\n153.2.3.2.7 Lane distribution <\/td>\n<\/tr>\n
93<\/td>\n153.2.3.3 Receive function
153.2.3.3.1 Lane lock and deskew
153.2.3.3.2 Lane reorder
153.2.3.3.3 De-scrambler
153.2.3.3.4 SC-FEC decoder
153.2.3.3.5 GMP demapper <\/td>\n<\/tr>\n
94<\/td>\n153.2.3.3.6 Block alignment
153.2.3.3.7 Block distribution
153.2.4 Detailed functions and state diagrams
153.2.4.1 State variables
153.2.4.1.1 Variables <\/td>\n<\/tr>\n
95<\/td>\n153.2.4.2 Functions <\/td>\n<\/tr>\n
96<\/td>\n153.2.4.3 Counters
153.2.4.4 State diagrams <\/td>\n<\/tr>\n
98<\/td>\n153.2.5 SC-FEC MDIO function mapping
153.2.5.1 FEC_corrected_cw_counter
153.2.5.2 FEC_uncorrected_cw_counter
153.2.5.3 FEC_total_bits_counter <\/td>\n<\/tr>\n
99<\/td>\n153.2.5.4 FEC_corrected_bits_counter
153.3 100GBASE-ZR PMA sublayer
153.3.1 100GBASE-ZR PMA service interface <\/td>\n<\/tr>\n
100<\/td>\n153.3.2 Functions within the 100GBASE-ZR PMA sublayer
153.3.2.1 Functional block diagram
153.3.2.2 Transmit function
153.3.2.2.1 Lane interleave
153.3.2.2.2 DQPSK encode <\/td>\n<\/tr>\n
101<\/td>\n153.3.2.3 Receive function
153.3.2.3.1 DQPSK decode
153.3.2.3.2 Lane de-interleave <\/td>\n<\/tr>\n
102<\/td>\n153.4 Protocol implementation conformance statement (PICS) proforma for Clause 153, SC-FEC and 100GBASE-ZR Physical Medium Attachment (PMA) sublayer for 100GBASE-ZR PHYs
153.4.1 Introduction
153.4.2 Identification
153.4.2.1 Implementation identification
153.4.2.2 Protocol summary <\/td>\n<\/tr>\n
103<\/td>\n153.4.3 Major capabilities\/options
153.4.4 PICS proforma tables for SC-FEC sublayer for 100GBASE-ZR PHYs
153.4.4.1 Transmit function <\/td>\n<\/tr>\n
104<\/td>\n153.4.4.2 Receive function
153.4.4.3 State diagrams <\/td>\n<\/tr>\n
105<\/td>\n154. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-ZR
154.1 Overview <\/td>\n<\/tr>\n
106<\/td>\n154.1.1 Bit error ratio <\/td>\n<\/tr>\n
107<\/td>\n154.2 Physical Medium Dependent (PMD) service interface
154.3 Delay and Skew
154.3.1 Delay constraints
154.3.2 Skew constraints <\/td>\n<\/tr>\n
108<\/td>\n154.4 PMD MDIO function mapping <\/td>\n<\/tr>\n
109<\/td>\n154.5 PMD functional specifications
154.5.1 PMD block diagram
154.5.2 PMD transmit function <\/td>\n<\/tr>\n
110<\/td>\n154.5.3 PMD receive function
154.5.4 PMD global signal detect function
154.5.5 PMD reset function
154.5.6 PMD global transmit disable function (optional)
154.5.7 PMD fault function (optional) <\/td>\n<\/tr>\n
111<\/td>\n154.5.8 PMD transmit fault function (optional)
154.5.9 PMD receive fault function (optional)
154.6 DWDM channel over a DWDM black link <\/td>\n<\/tr>\n
113<\/td>\n154.7 PMD to MDI optical specifications for 100GBASE-ZR <\/td>\n<\/tr>\n
114<\/td>\n154.7.1 100GBASE-ZR transmitter optical specifications <\/td>\n<\/tr>\n
115<\/td>\n154.7.2 100GBASE-ZR receive optical specifications
154.8 100GBASE-ZR DWDM black link transfer characteristics
154.9 Definition of optical parameters and measurement methods
154.9.1 Test patterns for optical parameters <\/td>\n<\/tr>\n
117<\/td>\n154.9.2 Optical center frequency (wavelength) and side-mode suppression ratio (SMSR)
154.9.3 Average channel output power
154.9.4 Spectral excursion
154.9.5 Laser linewidth <\/td>\n<\/tr>\n
118<\/td>\n154.9.6 Offset between the carrier and the nominal center frequency
154.9.7 Power difference between X and Y polarizations
154.9.8 Skew between X and Y polarizations
154.9.9 Error vector magnitude
154.9.10 I-Q offset
154.9.11 Optical signal-to-noise ratio (OSNR)
154.9.12 Transmitter in-band OSNR
154.9.13 Average receive power <\/td>\n<\/tr>\n
119<\/td>\n154.9.14 Receiver sensitivity
154.9.15 Receiver OSNR
154.9.16 Receiver OSNR tolerance
154.9.17 Ripple
154.9.18 Optical path OSNR penalty
154.9.19 Optical path power penalty
154.9.20 Polarization dependent loss <\/td>\n<\/tr>\n
120<\/td>\n154.9.21 Polarization rotation speed
154.9.22 Inter-channel crosstalk at TP3
154.9.23 Interferometric crosstalk at TP3
154.10 Safety, installation, environment, and labeling
154.10.1 General safety
154.10.2 Laser safety
154.10.3 Installation
154.10.4 Environment <\/td>\n<\/tr>\n
121<\/td>\n154.10.5 Electromagnetic emission
154.10.6 Temperature, humidity, and handling
154.10.7 PMD labeling requirements
154.11 Medium Dependent Interface (MDI) <\/td>\n<\/tr>\n
122<\/td>\n154.12 Protocol implementation conformance statement (PICS) proforma for Clause 154, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-ZR
154.12.1 Introduction
154.12.2 Identification
154.12.2.1 Implementation identification
154.12.2.2 Protocol summary <\/td>\n<\/tr>\n
123<\/td>\n154.12.3 Major capabilities\/options
154.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-ZR
154.12.4.1 PMD functional specifications <\/td>\n<\/tr>\n
124<\/td>\n154.12.4.2 Management functions
154.12.4.3 PMD to MDI optical specifications for 100GBASE-ZR <\/td>\n<\/tr>\n
125<\/td>\n154.12.4.4 Optical measurement methods
154.12.4.5 Environmental specifications
154.12.4.6 Characteristics of DWDM black link and MDI <\/td>\n<\/tr>\n
126<\/td>\nAnnex A (informative) Bibliography <\/td>\n<\/tr>\n
127<\/td>\nAnnex 83C (informative) PMA sublayer partitioning examples
83C.4 Partitioning examples with SC-FEC
83C.4.1 CAUI-4 with SC-FEC <\/td>\n<\/tr>\n
128<\/td>\nAnnex 135A (informative) 50 Gb\/s and 100 Gb\/s PMA sublayer partitioning examples
135A.3 Partitioning examples of 100GAUI-n with Inverse RS-FEC
135A.3.1 100GAUI-n with Inverse RS-FEC <\/td>\n<\/tr>\n
129<\/td>\n135A.3.2 CAUI-4 chip-to-chip and 100GAUI-n chip-to-module with Inverse RS-FEC <\/td>\n<\/tr>\n
130<\/td>\nAnnex 154A (informative) Examples of 100GBASE-ZR compliant DWDM black links
154A.1 Introduction <\/td>\n<\/tr>\n
131<\/td>\n154A.2 Relationship between OSNR and average optical power <\/td>\n<\/tr>\n
132<\/td>\n154A.3 Examples of DWDM black link applications with OSNR at TP3 between 19.5 dB (12.5 GHz) and 35 dB (12.5 GHz) <\/td>\n<\/tr>\n
133<\/td>\n154A.4 Example of DWDM black link applications with OSNR at TP3 greater than or equal to 35 dB (12.5 GHz) <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE\/ISO\/IEC International Standard -Telecommunications and exchange between information technology systems–Requirements for local and metropolitan area networks–Part 3: Standard for Ethernet AMENDMENT 13: Physical layers and management parameters for 100 Gb\/s operation over DWDM systems<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2022<\/td>\n136<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":415007,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-415001","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/415001","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/415007"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=415001"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=415001"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=415001"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}