{"id":293845,"date":"2024-10-19T19:58:16","date_gmt":"2024-10-19T19:58:16","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iso-iec-14165-1512017\/"},"modified":"2024-10-25T17:10:16","modified_gmt":"2024-10-25T17:10:16","slug":"bs-iso-iec-14165-1512017","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iso-iec-14165-1512017\/","title":{"rendered":"BS ISO\/IEC 14165-151:2017"},"content":{"rendered":"
This part of ISO\/IEC 14165 describes extensions to the Fibre Channel signaling and physical layer requirements defined in ISO\/IEC 14165\u2011142, Fibre Channel – Physical Interfaces 2, to transport Fibre Channel over the commonly available 4-pair balanced copper cablings specified in ISO\/IEC 11801:2002 and TIA\/EIA\u2011568\u2011B.2\u20112001. This standard is one of the Fibre Channel family of standards.<\/p>\n
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 3 Terms, definitions, abbreviations, symbols, and conventions 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 3.2 Editorial conventions 3.3 Abbreviations, acronyms, and symbols Tables Table 1 \u2013 ISO and American Conventions <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 3.4 Keywords <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 3.5 State Diagram notation 3.5.1 State Diagram conventions Figures Figure 1 \u2013 State diagram notation example <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 3.5.2 State Diagram variables 3.5.3 State Diagram timers 3.5.4 State transitions <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 3.5.5 Operators Table 2 \u2013 State Diagram Operators <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 4 Structure and concepts 4.1 Overview Figure 2 \u2013 FC-BaseT topology <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 4.2 Relationship with other standards Figure 3 \u2013 FC-BaseT relationship to the OSI Reference Model,the Fibre Channel Levels, and the IEEE 802.3 LAN Model Table 3 \u2013 FC-BaseT design goals for data rates and cable reachesfor the cabling channels specified by ISO\/IEC11801:2002\/AMD2:2010 <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 4.3 FC-BaseT PHY logical model Figure 4 \u2013 An FC-BaseT PHY logical model <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 4.4 FC-BaseT usage of XGMII Table 4 \u2013 XGMII frequencies for FC-BaseT Table 5 \u2013 XGMII characters <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 4.5 Operation of FC-BaseT 4.5.1 Overview Table 6 \u2013 FC-BaseT symbol and data rates <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 4.5.2 PCS overview Figure 5 \u2013 PCS and PMA functional block diagram <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 4.5.3 PMA overview 4.6 FC-BaseT service primitives and interfaces 4.6.1 Overview 4.6.2 PMA service interface 4.6.2.1 Overview <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 4.6.2.2 PMA_TXMODE.indication Figure 6 \u2013 PCS and PMA service interfaces <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 4.6.2.3 PMA_CONFIG.indication 4.6.2.4 PMA_UNITDATA.request <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 4.6.2.5 PMA_UNITDATA.indication 4.6.2.6 PMA_SCRSTATUS.request <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 4.6.2.7 PMA_PCSSTATUS.request 4.6.2.8 PMA_RXSTATUS.indication 4.6.2.9 PMA_REMRXSTATUS.request <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 4.6.3 Management function interface 4.6.3.1 Overview 4.6.3.2 PMA_LINK.request 4.6.3.3 PMA_LINK.indication <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 4.7 FC-BaseT Nomenclature Figure 7 \u2013 FC-BaseT nomenclature <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | 5 Physical Coding Sublayer (PCS) 5.1 Overview 5.2 PCS reset function Figure 8 \u2013 PCS reference diagram <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 5.3 PCS transmit function 5.3.1 Overview Figure 9 \u2013 PCS transmit bit ordering <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 5.3.2 36\/33 transcoding Table 7 \u2013 Fibre Channel words <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | Table 8 \u2013 XGMII representation of Fibre Channel words Table 9 \u2013 36\/33 transcoding Table 10 \u2013 36\/33 transcoding examples <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | 5.3.3 Error detecting code <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 5.3.4 PCS scrambling Figure 10 \u2013 Side-stream scrambler for the Master PHY <\/td>\n<\/tr>\n | ||||||
40<\/td>\n | Figure 11 \u2013 Side-stream scrambler for the Slave PHY <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | 5.3.5 Schl\u00e4fli Lattice coding Figure 12 \u2013 4D PAM-8 Schl\u00e4fli Lattice encoder <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | 5.3.6 Trellis coding Figure 13 \u2013 4D PAM-8 Trellis encoder Table 11 \u2013 Bit to symbols mapping <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 5.3.7 Generation of PMA training sequences Figure 14 \u2013 Generation of PMA training PAM-2 sequences Table 12 \u2013 PMA training sequences <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 5.4 PCS receive function 5.4.1 Overview Figure 15 \u2013 PCS receive bit ordering <\/td>\n<\/tr>\n | ||||||
45<\/td>\n | 5.4.2 Decoding Figure 16 \u2013 4D PAM-8 Schl\u00e4fli Lattice decoder <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 5.4.3 PCS descrambling Figure 17 \u2013 Side-stream descrambler for the Master PHY Figure 18 \u2013 Side-stream descrambler for the Slave PHY <\/td>\n<\/tr>\n | ||||||
47<\/td>\n | 5.4.4 33\/36 transcoding <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 5.4.5 PCS synchronization 5.5 State Diagrams Table 13 \u2013 PCS synchronization state variables <\/td>\n<\/tr>\n | ||||||
49<\/td>\n | Figure 19 \u2013 PCS synchronization state diagram <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | 6 PMA Sublayer and Medium Dependent Interface 6.1 PMA Overview Figure 20 \u2013 PMA Reference Diagram <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 6.2 PMA Functions 6.2.1 PMA Reset function 6.2.2 PMA Transmit function 6.2.3 PMA Receive Function <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 6.2.4 PHY Control Function <\/td>\n<\/tr>\n | ||||||
53<\/td>\n | Table 14 \u2013 Idle2 and Idle3 Ordered Sets <\/td>\n<\/tr>\n | ||||||
54<\/td>\n | Figure 21 \u2013 Example of Link Establishment <\/td>\n<\/tr>\n | ||||||
55<\/td>\n | 6.2.5 Link Monitor Function 6.2.6 Clock Recovery Function 6.2.7 State Diagrams Table 15 \u2013 PHY Control and Link Monitor State Variables <\/td>\n<\/tr>\n | ||||||
56<\/td>\n | Table 16 \u2013 PHY Control and Link Monitor Timers <\/td>\n<\/tr>\n | ||||||
57<\/td>\n | Figure 22 \u2013 PHY Control State Diagram <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 6.3 PMA Electrical Specification 6.3.1 Isolation and EMC Requirements 6.3.2 Test Modes 6.3.2.1 Overview Figure 23 \u2013 Link Monitor State Diagram <\/td>\n<\/tr>\n | ||||||
59<\/td>\n | Table 17 \u2013 Management Register Settings for Test Modes <\/td>\n<\/tr>\n | ||||||
60<\/td>\n | 6.3.2.2 Test Fixtures Figure 24 \u2013 Transmitter Test Fixture A Figure 25 \u2013 Transmitter Test Fixture B <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 6.3.3 Transmitter Electrical Specifications 6.3.3.1 Overview 6.3.3.2 Transmitter Output Droop Figure 26 \u2013 Test Mode 1 Output (not to scale) Table 18 \u2013 Disturbing Signal Frequency Table 19 \u2013 Droop Requirements <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 6.3.3.3 Transmitter Distortion 6.3.3.4 Transmitter Timing Jitter <\/td>\n<\/tr>\n | ||||||
63<\/td>\n | 6.3.3.5 Transmitter Power Spectral Density (PSD) and Power Level Figure 27 \u2013 4GFC-BaseT Transmitter PSD at 5dBm <\/td>\n<\/tr>\n | ||||||
64<\/td>\n | Figure 28 \u2013 2GFC-BaseT Transmitter PSD at 5dBm <\/td>\n<\/tr>\n | ||||||
65<\/td>\n | Figure 29 \u2013 1GFC-BaseT Transmitter PSD at 5dBm <\/td>\n<\/tr>\n | ||||||
66<\/td>\n | 6.3.3.6 Transmitter Power Schedule 6.3.3.7 Transmit Clock Frequency 6.3.4 Receiver Electrical Specifications 6.3.4.1 Overview 6.3.4.2 Receiver Differential Input Signals Table 20 \u2013 Transmitter Power Schedule Table 21 \u2013 Transmitter Frequency Requirements <\/td>\n<\/tr>\n | ||||||
67<\/td>\n | 6.3.4.3 Receiver Frequency Tolerance 6.3.4.4 Alien Crosstalk Noise Rejection Table 23 \u2013 Alien Noise Requirements Table 22 \u2013 Receiver Frequency Requirements <\/td>\n<\/tr>\n | ||||||
68<\/td>\n | 6.4 MDI Specification 6.4.1 Overview 6.4.2 MDI Mechanical Specification Figure 30 \u2013 MDI Jack Connector Figure 31 \u2013 Balanced Cabling Plug Connector <\/td>\n<\/tr>\n | ||||||
69<\/td>\n | 6.4.3 Automatic MDI\/MDI-X Configuration 6.4.4 MDI Electrical Specification 6.4.5 MDI Fault tolerance 6.5 Link Segment Characteristics 6.5.1 Overview Table 24 \u2013 Assignment of PMA Signals to MDI and MDI-X Contacts Table 25 \u2013 FC-BaseT MDI Electrical Requirements <\/td>\n<\/tr>\n | ||||||
70<\/td>\n | 6.5.2 FC-BaseT Link Topology 6.5.3 FC-BaseT Cable Plant Requirements Figure 32 \u2013 FC-BaseT Link Topology Table 26 \u2013 FC-BaseT Cable Plant Requirements <\/td>\n<\/tr>\n | ||||||
71<\/td>\n | 7 Elasticity FIFO 7.1 Overview Figure 33 \u2013 FC-BaseT elasticity FIFO <\/td>\n<\/tr>\n | ||||||
72<\/td>\n | 7.2 Ordered sets processing Figure 34 \u2013 Example of E-FIFO implementation Table 27 \u2013 Extended Fill Words <\/td>\n<\/tr>\n | ||||||
73<\/td>\n | 7.3 Clock skew compensation Figure 35 \u2013 FC-BaseT clock skew compensation <\/td>\n<\/tr>\n | ||||||
75<\/td>\n | 8 PHY startup procedure 8.1 Overview 8.2 Host speeds determination 8.3 Host synchronization <\/td>\n<\/tr>\n | ||||||
76<\/td>\n | 8.4 FC-BaseT auto-negotiation 8.4.1 Overview <\/td>\n<\/tr>\n | ||||||
77<\/td>\n | 8.4.2 FC-BaseT support Figure 36 \u2013 Base page encoding Table 28 \u2013 Technology Ability Field <\/td>\n<\/tr>\n | ||||||
78<\/td>\n | 8.4.3 Master-Slave relationship Figure 37 \u2013 Unformatted page encoding Table 29 \u2013 Unformatted code field of the first unformatted page <\/td>\n<\/tr>\n | ||||||
79<\/td>\n | 8.4.4 Cable length estimation Table 30 \u2013 Master-Slave seed assignment <\/td>\n<\/tr>\n | ||||||
80<\/td>\n | 8.4.5 Tentative Operating Speed Determination Table 31 \u2013 Unformatted code field of the second unformatted page <\/td>\n<\/tr>\n | ||||||
81<\/td>\n | 8.4.6 Configuration resolution Table 32 \u2013 Unformatted code field of the third unformatted page <\/td>\n<\/tr>\n | ||||||
82<\/td>\n | 8.5 Speed downshift function 8.6 State diagrams <\/td>\n<\/tr>\n | ||||||
83<\/td>\n | Table 33 \u2013 Cable length estimation state variables (part 1 of 3) <\/td>\n<\/tr>\n | ||||||
85<\/td>\n | Table 34 \u2013 Cable length estimation timers <\/td>\n<\/tr>\n | ||||||
86<\/td>\n | Figure 38 \u2013 Clock detect state diagram <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | Figure 39 \u2013 Clock loopback state diagram <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | 9 Port management 9.1 Overview 9.2 FC-BaseT management registers Table 35 \u2013 FC-BaseT registers (part 1 of 2) <\/td>\n<\/tr>\n | ||||||
90<\/td>\n | 9.3 Control Register Table 36 \u2013 FC-BaseT control register bits (part 1 of 3) <\/td>\n<\/tr>\n | ||||||
93<\/td>\n | 9.4 Status Register Table 37 \u2013 FC-BaseT status register bits (part 1 of 3) <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | 9.5 Speed Downshift Register Table 38 \u2013 FC-BaseT speed downshift register bits <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | 9.6 Test Register 9.7 SNR Margin Registers Table 39 \u2013 FC-BaseT test register bits Table 40 \u2013 FC-BaseT SNR margin registers bits (part 1 of 2) <\/td>\n<\/tr>\n | ||||||
97<\/td>\n | 9.8 Auto-Negotiation Pages Registers <\/td>\n<\/tr>\n | ||||||
98<\/td>\n | Table 41 \u2013 FC-BaseT auto-negotiation pages registers bits (part 1 of 2) <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | Annex A A.1 Overview A.2 Notation A.3 Additional mappings Table A.1 \u2013 Additional 36\/33 mappings <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | Table A.2 \u2013 6-bit encoding of XGMII control characters <\/td>\n<\/tr>\n | ||||||
102<\/td>\n | Annex B Figure B.1 \u2013 4D symbol error rate in function of SNR <\/td>\n<\/tr>\n | ||||||
104<\/td>\n | Annex C Table C.1 \u2013 Recommended transmitter power schedule <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Information technology. Fibre channel – Fibre Channel BaseT (FC-BaseT)<\/b><\/p>\n |