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IEEE 1838-2019

IEEE 1838-2019

$59.58

IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

Published By Publication Date Number of Pages
IEEE 2019 73
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New IEEE Standard – Active. IEEE Std 1838 is a die-centric standard; it applies to a die that is intended to be part of a multi-die stack. This standard defines die-level features that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks in both pre-packaging, post-packaging, and board-level situations. The primary focus of inter-die interconnect technology addressed by this standard is through-silicon vias (TSVs); however, this does not preclude its use with other interconnect technologies such as wire-bonding

PDF Catalog

PDF Pages PDF Title
1 IEEE Std 1838™-2019 Front cover
2 Title page
4 Important Notices and Disclaimers Concerning IEEE Standards Documents
7 Participants
9 Introduction
10 Contents
11 List of Figures
13 List of Tables
14 1. Overview
1.1 Scope
15 1.2 Three-dimensional integrated circuits (ICs) stacking technology
16 1.3 Motivation for a 3D-DfT standard
1.4 Context
1.5 Organization of the standard
17 1.6 Word usage
2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions
22 3.2 Acronyms and abbreviations
24 4. Technology
4.1 Stack model
25 4.2 Wafer-level die access
26 4.3 Physical attributes
27 5. Serial test access ports
5.1 Primary test access port
29 5.2 Primary test access port controller
31 5.3 Secondary test access port (STAP)
32 5.4 Secondary test access port control logic
36 5.5 Registers
42 5.6 Configuration elements
43 6. Die wrapper register
6.1 Register design
48 6.2 DWR cell structure and operation
49 6.3 DWR operation events
50 6.4 DWR operation modes
52 6.5 Parallel access to the DWR
53 6.6 DWR cell naming
54 6.7 DWR cell examples
57 6.8 Wrapper states
58 7. Flexible parallel port
7.1 General introduction
61 7.2 FPP lane examples
63 7.3 Structure of the FPP
67 7.4 Allocation of FPP configuration elements to the FPP lane control terminals
8. IEEE Std 1838 DWR relationship with other standards
69 Annex A (informative) Bubble diagrams
71 Annex B (informative) Bibliography
73 Back cover

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IEEE 1838-2019
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