IEEE 1685-2014

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IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows (Superseded)

Published By	Publication Date	Number of Pages
IEEE	2014

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Description

Revision Standard – Superseded. Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C(R)) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations. (The PDF of this standard is available in the GETIEEE program. The “IEEE Get Program” grants public access to view and download individual PDFs of select standards at no charge. Visit https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1685-2014 Front Cover
3	Title page
5	Important Notices and Disclaimers Concerning IEEE Standards Documents
8	Participants
9	Introduction
10	Contents
13	IMPORTANT NOTICE 1. Overview 1.1 Scope
14	1.2 Purpose 1.3 Design environment 1.3.1 IP-XACT design environment
15	1.3.2 IP-XACT object descriptions 1.3.3 Object interactions
16	1.3.4 IP-XACT generators 1.3.5 IP-XACT design environment interfaces
17	1.3.6 Tight generator interface 1.3.7 Design intellectual property
18	1.4 IP-XACT–enabled implementations 1.4.1 Design environments
19	1.4.2 Point tools 1.4.3 IPs 1.4.4 Generators 1.5 Conventions used 1.5.1 Visual cues (meta-syntax)
20	1.5.2 Notational conventions 1.5.3 Syntax examples 1.5.4 Graphics used to document the schema
24	1.6 Use of color in this standard 1.7 Contents of this standard
25	2. Normative references
27	3. Definitions, acronyms, and abbreviations 3.1 Definitions
32	3.2 Acronyms and abbreviations
33	4. Interoperability use model 4.1 Roles and responsibilities 4.1.1 Component IP provider 4.1.2 SoC design IP provider 4.1.3 SoC design IP consumer 4.1.4 Design tool supplier
34	4.2 IP-XACT IP exchange flows 4.2.1 Component or SoC design IP provider use model
35	4.2.2 Generator provider use model 4.2.3 System design tool provider use model
37	5. Interface definition descriptions 5.1 Definition descriptions
38	5.2 Bus definition 5.2.1 Schema 5.2.2 Description
40	5.3 Abstraction definition 5.3.1 Schema 5.3.2 Description
41	5.4 Ports 5.4.1 Schema 5.4.2 Description
42	5.5 Wire ports 5.5.1 Schema 5.5.2 Description
43	5.6 Qualifiers 5.6.1 Schema 5.6.2 Description
44	5.7 Wire port group 5.7.1 Schema
45	5.7.2 Description 5.8 Wire port mode (and mirrored mode) constraints 5.8.1 Schema
46	5.8.2 Description 5.9 Transactional ports 5.9.1 Schema 5.9.2 Description
48	5.10 Transactional port group 5.10.1 Schema 5.10.2 Description
49	5.11 Extending bus and abstraction definitions 5.11.1 Extending bus definitions 5.11.2 Extending abstraction definitions
50	5.11.3 Modifying definitions
51	5.12 Clock and reset handling
53	6. Component descriptions 6.1 Component 6.1.1 Schema 6.1.2 Description
55	6.2 Interfaces 6.2.1 Direct interface modes
56	6.2.2 Mirrored interface modes 6.2.3 Monitor interface modes 6.3 Interface interconnections 6.3.1 Direct connection 6.3.2 Mirrored-non-mirrored connection 6.3.3 Monitor connection
57	6.3.4 Broadcast connections 6.3.5 Interface logical to physical port mapping
58	6.4 Complex interface interconnections 6.4.1 Channel
59	6.4.2 Bridge
60	6.5 Bus interfaces 6.5.1 busInterface
62	6.5.2 Interface modes
64	6.5.3 Master interface
65	6.5.4 Slave interface
66	6.5.5 Mirrored slave interface
67	6.5.6 Abstraction types
68	6.5.7 Port map
70	6.6 Indirect interfaces 6.6.1 Schema 6.6.2 Description
71	6.7 Component channels 6.7.1 Schema
72	6.7.2 Description 6.8 Address spaces
73	6.8.1 addressSpaces
74	6.8.2 Segments
75	6.8.3 executableImage
76	6.8.4 languageTools
78	6.8.5 fileBuilder
79	6.8.6 Local memory map
80	6.9 Memory maps 6.9.1 memoryMaps
81	6.9.2 Address block
82	6.9.3 Address block definition group
83	6.9.4 memoryBlockData group
85	6.9.5 Bank
87	6.9.6 Banked address block
88	6.9.7 Banked bank
89	6.9.8 Banked subspace
90	6.9.9 Subspace map
91	6.10 Remapping 6.10.1 Memory remap
92	6.10.2 Remap states
93	6.11 Registers 6.11.1 Register data
94	6.11.2 Register
95	6.11.3 Register definition group
96	6.11.4 Alternate registers
97	6.11.5 Alternate register definition group
99	6.11.6 Register file
100	6.11.7 Register file definition group
101	6.11.8 Register bit fields
103	6.11.9 Field data group
105	6.11.10 Enumeration values
106	6.11.11 Write value constraint
107	6.12 Models 6.12.1 Model
109	6.12.2 instantiationsGroup
110	6.12.3 componentInstantiation
112	6.12.4 designInstantiation
113	6.12.5 designConfigurationInstantiation
114	6.12.6 Module parameters
117	6.12.7 Component ports
118	6.12.8 Component wire ports
120	6.12.9 Component wireTypeDef
122	6.12.10 Component driver
124	6.12.11 Component driver/clockDriver
125	6.12.12 Implementation constraints
126	6.12.13 Component wire port constraints
127	6.12.14 Port timing constraints
128	6.12.15 Load and drive constraint cell specification
129	6.12.16 Other clock drivers
130	6.12.17 Component transactional port type
131	6.12.18 Component transactional protocol/payload definition
132	6.12.19 Component transactional port type definition
133	6.12.20 Component transactional port service 6.12.21 Phantom ports
134	6.13 Component generators 6.13.1 Schema
135	6.13.2 Description
136	6.14 Choices 6.14.1 Schema 6.14.2 Description
137	6.15 File sets 6.15.1 fileSets
138	6.15.2 file
140	6.15.3 buildCommand
141	6.15.4 defaultFileBuilder
142	6.15.5 function
143	6.15.6 sourceFile 6.16 White box elements
144	6.16.1 Schema 6.16.2 Description
145	6.17 White box element reference 6.17.1 Schema 6.17.2 Description
146	6.18 CPUs 6.18.1 Schema 6.18.2 Description
147	6.19 Reset types 6.19.1 Schema 6.19.2 Description
149	7. Design descriptions 7.1 Design 7.1.1 Schema 7.1.2 Description
150	7.2 Design component instances 7.2.1 Schema 7.2.2 Description
151	7.3 Design interconnections 7.3.1 interconnection
152	7.3.2 monitorInterconnection
153	7.4 Active, hierarchical, monitored, and monitor interfaces 7.4.1 Schema
155	7.4.2 Description
156	7.5 Design ad hoc connections 7.5.1 Schema 7.5.2 Description
157	7.5.3 Ad hoc wire connection 7.5.4 Ad hoc transactional connection 7.5.5 Interaction rules between an interface-based connection and ad hoc connections
158	7.6 Port references 7.6.1 Schema 7.6.2 Description
161	8. Abstractor descriptions 8.1 Abstractor 8.1.1 Schema
162	8.1.2 Description
163	8.2 Abstractor interfaces 8.2.1 Schema 8.2.2 Description
164	8.3 Abstractor models 8.3.1 Schema 8.3.2 Description 8.4 Abstractor views 8.4.1 Schema
165	8.4.2 Description 8.5 Abstractor ports 8.5.1 Schema
166	8.5.2 Description
167	8.6 Abstractor wire ports 8.6.1 Schema 8.6.2 Description
168	8.7 Abstractor generators 8.7.1 Schema
169	8.7.2 Description
171	9. Generator chain descriptions 9.1 generatorChain 9.1.1 Schema
172	9.1.2 Description
173	9.2 generatorChainSelector 9.2.1 Schema 9.2.2 Description
174	9.3 generatorChain component selector 9.3.1 Schema 9.3.2 Description
175	9.4 generatorChain generator 9.4.1 Schema 9.4.2 Description
177	10. Design configuration descriptions 10.1 Design configuration
178	10.2 designConfiguration 10.2.1 Schema 10.2.2 Description
179	10.3 interconnectionConfiguration 10.3.1 Schema 10.3.2 Description
180	10.4 abstractorInstance 10.4.1 Schema
181	10.4.2 Description 10.5 viewConfiguration 10.5.1 Schema 10.5.2 Description
183	11. Catalog descriptions 11.1 catalog 11.1.1 Schema
184	11.1.2 Description
185	11.2 ipxactFile 11.2.1 Schema 11.2.2 Description
187	12. Addressing 12.1 Calculating the bit address of a bit in a memory map
189	12.2 Calculating the bus address at the slave bus interface 12.3 Calculating the address at the indirect interface
190	12.4 Address modifications of a channel 12.5 Addressing in the master 12.6 Address translation in a bridge
192	13. Data visibility 13.1 Mapped address bits mask 13.2 Address modifications of an interconnection 13.3 Bit steering in a channel
193	13.4 Visibility of bits 13.4.1 Visible address ranges 13.4.2 Bit lanes in memory maps
194	13.4.3 Bit lanes in address spaces 13.4.4 Bit lanes in bus interfaces 13.4.5 Bit lanes in channels 13.4.6 Bit steering in masters and slaves
197	Annex A (informative) Bibliography
199	Annex B (normative) Semantic consistency rules
229	Annex C (normative) Common elements and concepts
263	Annex D (normative) Types
265	Annex E (normative) SystemVerilog expressions
279	Annex F (normative) Tight generator interface
471	Annex G (informative) External bus with an internal/digital interface
473	Annex H (informative) Bridges and channels
483	Annex I (informative) Examples
510	Back Cover

Additional information

Standard Title	IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows (Superseded)
Published Code	IEEE
Publication Date	2014

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IEEE 1685-2014

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