IEEE 1364 2001

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IEEE Standard Verilog Hardware Description Language

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IEEE	2001	879

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Description

Revision Standard – Inactive – Superseded. Supersedes 1364-1995.

PDF Catalog

PDF Pages	PDF Title
1	Cover Page
2	Title Page
4	About IEEE Std 1364-2001 Version C and the Errata
5	Participants—Version C and Errata
6	Introduction
8	Participants
10	CONTENTS
24	1. Overview 1.1 Objectives of this standard 1.2 Conventions used in this standard
25	1.3 Syntactic description 1.4 Contents of this standard
27	1.5 Header file listings
28	1.6 Examples 1.7 Prerequisites
29	2. Lexical conventions 2.1 Lexical tokens 2.2 White space 2.3 Comments 2.4 Operators 2.5 Numbers
30	2.5.1 Integer constants
33	2.5.2 Real constants 2.5.3 Conversion 2.6 Strings
34	2.6.1 String variable declaration 2.6.2 String manipulation 2.6.3 Special characters in strings
35	2.7 Identifiers, keywords, and system names 2.7.1 Escaped identifiers
36	2.7.2 Generated identifiers 2.7.3 Keywords 2.7.4 System tasks and functions
37	2.7.5 Compiler directives 2.8 Attributes
38	2.8.1 Examples
39	2.8.2 Syntax
43	3. Data types 3.1 Value set 3.2 Nets and variables 3.2.1 Net declarations
45	3.2.2 Variable declarations
46	3.3 Vectors 3.3.1 Specifying vectors
47	3.3.2 Vector net accessibility 3.4 Strengths 3.4.1 Charge strength 3.4.2 Drive strength
48	3.5 Implicit declarations 3.6 Net initialization 3.7 Net types 3.7.1 Wire and tri nets
49	3.7.2 Wired nets 3.7.3 Trireg net
50	3.7.3.1 Capacitive networks
53	3.7.3.2 Ideal capacitive state and charge decay 3.7.4 Tri0 and tri1 nets
54	3.7.5 Supply nets 3.8 Regs 3.9 Integers, reals, times, and realtimes
55	3.9.1 Operators and real numbers 3.9.2 Conversion
56	3.10 Arrays 3.10.1 Net arrays 3.10.2 reg and variable arrays 3.10.3 Memories
57	3.10.3.1 Array examples 3.10.3.1.1 Array declarations 3.10.3.1.2 Assignment to array elements 3.10.3.1.3 Memory differences 3.11 Parameters
58	3.11.1 Module parameters
59	3.11.2 Local parameters – localparam
60	3.11.3 Specify parameters
61	3.12 Name spaces
63	4. Expressions 4.1 Operators
64	4.1.1 Operators with real operands
65	4.1.2 Operator precedence
66	4.1.3 Using integer numbers in expressions 4.1.4 Expression evaluation order
67	4.1.5 Arithmetic operators
68	4.1.6 Arithmetic expressions with regs and integers
69	4.1.7 Relational operators 4.1.8 Equality operators
70	4.1.9 Logical operators 4.1.10 Bit-wise operators
71	4.1.11 Reduction operators
72	4.1.12 Shift operators
73	4.1.13 Conditional operator
74	4.1.14 Concatenations
75	4.1.15 Event or 4.2 Operands 4.2.1 Vector bit-select and part-select addressing
77	4.2.2 Array and memory addressing
78	4.2.3 Strings
79	4.2.3.1 String operations 4.2.3.2 String value padding and potential problems
80	4.2.3.3 Null string handling 4.3 Minimum, typical, and maximum delay expressions
82	4.4 Expression bit lengths 4.4.1 Rules for expression bit lengths
83	4.4.2 An example of an expression bit-length problem
84	4.4.3 Example of self-determined expressions
85	4.5 Signed expressions 4.5.1 Rules for expression types 4.5.2 Steps for evaluating an expression
86	4.5.3 Steps for evaluating an assignment 4.5.4 Handling X and Z in signed expressions
87	5. Scheduling semantics 5.1 Execution of a model 5.2 Event simulation 5.3 The stratified event queue
88	5.4 The Verilog simulation reference model
89	5.4.1 Determinism 5.4.2 Nondeterminism 5.5 Race conditions 5.6 Scheduling implication of assignments
90	5.6.1 Continuous assignment 5.6.2 Procedural continuous assignment 5.6.3 Blocking assignment 5.6.4 Nonblocking assignment 5.6.5 Switch (transistor) processing
91	5.6.6 Port connections 5.6.7 Functions and tasks
92	6. Assignments 6.1 Continuous assignments
93	6.1.1 The net declaration assignment 6.1.2 The continuous assignment statement
95	6.1.3 Delays 6.1.4 Strength
96	6.2 Procedural assignments 6.2.1 Variable declaration assignment
97	6.2.2 Variable declaration syntax
98	7. Gate and switch level modeling 7.1 Gate and switch declaration syntax
100	7.1.1 The gate type specification 7.1.2 The drive strength specification
101	7.1.3 The delay specification 7.1.4 The primitive instance identifier 7.1.5 The range specification
102	7.1.6 Primitive instance connection list
104	7.2 and, nand, nor, or, xor, and xnor gates
105	7.3 buf and not gates
106	7.4 bufif1, bufif0, notif1, and notif0 gates
107	7.5 MOS switches
109	7.6 Bidirectional pass switches 7.7 CMOS switches
110	7.8 pullup and pulldown sources
111	7.9 Logic strength modeling
112	7.10 Strengths and values of combined signals 7.10.1 Combined signals of unambiguous strength
113	7.10.2 Ambiguous strengths: sources and combinations
118	7.10.3 Ambiguous strength signals and unambiguous signals
122	7.10.4 Wired logic net types
125	7.11 Strength reduction by nonresistive devices 7.12 Strength reduction by resistive devices 7.13 Strengths of net types 7.13.1 tri0 and tri1 net strengths 7.13.2 trireg strength 7.13.3 supply0 and supply1 net strengths
126	7.14 Gate and net delays
127	7.14.1 min:typ:max delays
128	7.14.2 trireg net charge decay 7.14.2.1 The charge decay process 7.14.2.2 The delay specification for charge decay time
130	8. User-defined primitives (UDPs) 8.1 UDP definition
132	8.1.1 UDP header 8.1.2 UDP port declarations 8.1.3 Sequential UDP initial statement 8.1.4 UDP state table
133	8.1.5 Z values in UDP 8.1.6 Summary of symbols
134	8.2 Combinational UDPs
135	8.3 Level-sensitive sequential UDPs 8.4 Edge-sensitive sequential UDPs
136	8.5 Sequential UDP initialization
138	8.6 UDP instances
139	8.7 Mixing level-sensitive and edge-sensitive descriptions
140	8.8 Level-sensitive dominance
141	9. Behavioral modeling 9.1 Behavioral model overview
142	9.2 Procedural assignments 9.2.1 Blocking procedural assignments
144	9.2.2 The nonblocking procedural assignment
147	9.3 Procedural continuous assignments
148	9.3.1 The assign and deassign procedural statements
149	9.3.2 The force and release procedural statements
150	9.4 Conditional statement
151	9.4.1 If-else-if construct
153	9.5 Case statement
156	9.5.1 Case statement with don’t-cares 9.5.2 Constant expression in case statement
157	9.6 Looping statements
159	9.7 Procedural timing controls
160	9.7.1 Delay control
161	9.7.2 Event control 9.7.3 Named events
162	9.7.4 Event or operator
163	9.7.5 Implicit event_expression list
164	9.7.6 Level sensitive event control
165	9.7.7 Intra-assignment timing controls
169	9.8 Block statements 9.8.1 Sequential blocks
170	9.8.2 Parallel blocks
171	9.8.3 Block names 9.8.4 Start and finish times
172	9.9 Structured procedures
173	9.9.1 Initial construct 9.9.2 Always construct
175	10. Tasks and functions 10.1 Distinctions between tasks and functions 10.2 Tasks and task enabling
176	10.2.1 Task declarations
177	10.2.2 Task enabling and argument passing
179	10.2.3 Task memory usage and concurrent activation
180	10.3 Functions and function calling
181	10.3.1 Function declarations
182	10.3.2 Returning a value from a function
183	10.3.3 Calling a function 10.3.4 Function rules
184	10.3.5 Use of constant functions
186	11. Disabling of named blocks and tasks
189	12. Hierarchical structures 12.1 Modules
191	12.1.1 Top level modules 12.1.2 Module instantiation
193	12.1.3 Generated instantiation
196	12.1.3.1 genvar – generate statement index variable 12.1.3.2 generate-loop
200	12.1.3.3 generate-conditional
201	12.1.3.4 generate-case
203	12.2 Overriding module parameter values
205	12.2.1 defparam statement
206	12.2.2 Module instance parameter value assignment 12.2.2.1 Parameter value assignment by ordered list
207	12.2.2.2 Parameter value assignment by name
208	12.2.3 Parameter dependence 12.3 Ports 12.3.1 Port definition 12.3.2 List of ports
209	12.3.3 Port declarations
211	12.3.4 List of ports declarations 12.3.5 Connecting module instance ports by ordered list
212	12.3.6 Connecting module instance ports by name
213	12.3.7 Real numbers in port connections
214	12.3.8 Connecting dissimilar ports 12.3.9 Port connection rules 12.3.9.1 Rule 1 12.3.9.2 Rule 2
215	12.3.10 Net types resulting from dissimilar port connections 12.3.10.1 Net type resolution rule 12.3.10.2 Net type table
216	12.3.11 Connecting signed values via ports 12.4 Hierarchical names
219	12.5 Upwards name referencing
221	12.6 Scope rules
223	13. Configuring the contents of a design 13.1 Introduction 13.1.1 Library notation
224	13.1.2 Basic configuration elements 13.2 Libraries 13.2.1 Specifying libraries – the library map file
225	13.2.1.1 File path resolution
226	13.2.2 Using multiple library mapping files 13.2.3 Mapping source files to libraries 13.3 Configurations 13.3.1 Basic configuration syntax
227	13.3.1.1 Design statement 13.3.1.2 The default clause 13.3.1.3 The instance clause
228	13.3.1.4 The cell clause 13.3.1.5 The liblist clause
229	13.3.1.6 The use clause 13.3.2 Hierarchical configurations
230	13.4 Using libraries and configs 13.4.1 Precompiling in a single-pass use-model 13.4.2 Elaboration-time compiling in a single-pass use-model 13.4.3 Precompiling using a separate compilation tool 13.4.4 Command line considerations
231	13.5 Configuration examples 13.5.1 Default configuration from library map file 13.5.2 Using the default clause
232	13.5.3 Using the cell clause 13.5.4 Using the instance clause 13.5.5 Using a hierarchical config
233	13.6 Displaying library binding information 13.7 Library mapping examples 13.7.1 Using the command line to control library searching 13.7.2 File path specification examples
234	13.7.3 Resolving multiple path specifications
235	14. Specify blocks 14.1 Specify block declaration
236	14.2 Module path declarations
237	14.2.1 Module path restrictions 14.2.2 Simple module paths
238	14.2.3 Edge-sensitive paths
239	14.2.4 State-dependent paths 14.2.4.1 Conditional expression
240	14.2.4.2 Simple state-dependent paths
241	14.2.4.3 Edge-sensitive state-dependent paths
242	14.2.4.4 The ifnone condition
243	14.2.5 Full connection and parallel connection paths
244	14.2.6 Declaring multiple module paths in a single statement
245	14.2.7 Module path polarity 14.2.7.1 Unknown polarity 14.2.7.2 Positive polarity
246	14.2.7.3 Negative polarity 14.3 Assigning delays to module paths
247	14.3.1 Specifying transition delays on module paths
248	14.3.2 Specifying x transition delays
249	14.3.3 Delay selection
250	14.4 Mixing module path delays and distributed delays
251	14.5 Driving wired logic
252	14.6 Detailed control of pulse filtering behavior
253	14.6.1 Specify block control of pulse limit values
254	14.6.2 Global control of pulse limit values 14.6.3 SDF annotation of pulse limit values
255	14.6.4 Detailed pulse control capabilities 14.6.4.1 On-event versus on-detect pulse filtering
256	14.6.4.2 Negative pulse detection
261	15. Timing checks 15.1 Overview
264	15.2 Timing checks using a stability window
265	15.2.1 $setup 15.2.2 $hold
266	15.2.3 $setuphold
268	15.2.4 $removal
269	15.2.5 $recovery
270	15.2.6 $recrem
272	15.3 Timing checks for clock and control signals
273	15.3.1 $skew
274	15.3.2 $timeskew
276	15.3.3 $fullskew
278	15.3.4 $width
279	15.3.5 $period
280	15.3.6 $nochange
281	15.4 Edge-control specifiers
283	15.5 Notifiers: user-defined responses to timing violations
285	15.5.1 Requirements for accurate simulation
287	15.5.2 Conditions in negative timing checks
289	15.5.3 Notifiers in negative timing checks 15.5.4 Option behavior 15.6 Enabling timing checks with conditioned events
290	15.7 Vector signals in timing checks
291	15.8 Negative timing checks
293	16. Backannotation using the Standard Delay Format (SDF) 16.1 The SDF annotator 16.2 Mapping of SDF constructs to Verilog 16.2.1 Mapping of SDF delay constructs to Verilog declarations
295	16.2.2 Mapping of SDF timing check constructs to Verilog
296	16.2.3 SDF annotation of specparams
297	16.2.4 SDF annotation of interconnect delays
298	16.3 Multiple annotations
299	16.4 Multiple SDF files 16.5 Pulse limit annotation
300	16.6 SDF to Verilog delay value mapping
301	17. System tasks and functions 17.1 Display system tasks
302	17.1.1 The display and write tasks 17.1.1.1 Escape sequences for special characters
303	17.1.1.2 Format specifications
305	17.1.1.3 Size of displayed data
306	17.1.1.4 Unknown and high impedance values
307	17.1.1.5 Strength format
309	17.1.1.6 Hierarchical name format 17.1.1.7 String format 17.1.2 Strobed monitoring
310	17.1.3 Continuous monitoring 17.2 File input-output system tasks and functions 17.2.1 Opening and closing files
312	17.2.2 File output system tasks
313	17.2.3 Formatting data to a string
314	17.2.4 Reading data from a file 17.2.4.1 Reading a character at a time 17.2.4.2 Reading a line at a time 17.2.4.3 Reading formatted data
317	17.2.4.4 Reading binary data
318	17.2.5 File positioning 17.2.6 Flushing output 17.2.7 I/O error status
319	17.2.8 Loading memory data from a file
320	17.2.9 Loading timing data from an SDF file
321	17.3 Timescale system tasks 17.3.1 $printtimescale
322	17.3.2 $timeformat
325	17.4 Simulation control system tasks 17.4.1 $finish 17.4.2 $stop
326	17.5 PLA modeling system tasks 17.5.1 Array types
327	17.5.2 Array logic types 17.5.3 Logic array personality declaration and loading 17.5.4 Logic array personality formats
330	17.6 Stochastic analysis tasks 17.6.1 $q_initialize
331	17.6.2 $q_add 17.6.3 $q_remove 17.6.4 $q_full 17.6.5 $q_exam
332	17.6.6 Status codes 17.7 Simulation time system functions 17.7.1 $time
333	17.7.2 $stime 17.7.3 $realtime
334	17.8 Conversion functions
335	17.9 Probabilistic distribution functions 17.9.1 $random function
336	17.9.2 $dist_ functions
337	17.9.3 Algorithm for probabilistic distribution functions
344	17.10 Command line input
345	17.10.1 $test$plusargs (string) 17.10.2 $value$plusargs (user_string, variable)
348	18. Value change dump (VCD) files 18.1 Creating the four state value change dump file 18.1.1 Specifying the name of the dump file ($dumpfile)
349	18.1.2 Specifying the variables to be dumped ($dumpvars)
350	18.1.3 Stopping and resuming the dump ($dumpoff/$dumpon)
351	18.1.4 Generating a checkpoint ($dumpall) 18.1.5 Limiting the size of the dump file ($dumplimit)
352	18.1.6 Reading the dump file during simulation ($dumpflush)
353	18.2 Format of the four state VCD file 18.2.1 Syntax of the four state VCD file
355	18.2.2 Formats of variable values
356	18.2.3 Description of keyword commands 18.2.3.1 $comment 18.2.3.2 $date
357	18.2.3.3 $enddefinitions 18.2.3.4 $scope
358	18.2.3.5 $timescale 18.2.3.6 $upscope 18.2.3.7 $version
359	18.2.3.8 $var
360	18.2.3.9 $dumpall 18.2.3.10 $dumpoff 18.2.3.11 $dumpon
361	18.2.3.12 $dumpvars
362	18.2.4 Four state VCD file format example
363	18.3 Creating the extended value change dump file 18.3.1 Specifying the dumpfile name and the ports to be dumped ($dumpports)
364	18.3.2 Stopping and resuming the dump ($dumpportsoff/$dumpportson)
365	18.3.3 Generating a checkpoint ($dumpportsall) 18.3.4 Limiting the size of the dump file ($dumpportslimit)
366	18.3.5 Reading the dump file during simulation ($dumpportsflush) 18.3.6 Description of keyword commands 18.3.6.1 $vcdclose
367	18.3.7 General rules for extended VCD system tasks 18.4 Format of the extended VCD file 18.4.1 Syntax of the extended VCD file
369	18.4.2 Extended VCD node information
371	18.4.3 Value changes 18.4.3.1 State characters
372	18.4.3.2 Drivers 18.4.4 Extended VCD file format example
374	19. Compiler directives 19.1 `celldefine and `endcelldefine 19.2 `default_nettype
375	19.3 `define and `undef 19.3.1 `define
377	19.3.2 `undef 19.4 `ifdef, `else, `elsif, `endif, `ifndef
381	19.5 `include 19.6 `resetall 19.7 `line
382	19.8 `timescale
384	19.9 `unconnected_drive and `nounconnected_drive
385	20. PLI overview 20.1 PLI purpose and history (informative) 20.2 User-defined system task or function names
386	20.3 User-defined system task or function types 20.4 Overriding built-in system task and function names 20.5 User-supplied PLI applications 20.6 PLI interface mechanism
387	20.7 User-defined system task and function arguments 20.8 PLI include files 20.9 PLI Memory Restrictions
388	21. PLI TF and ACC interface mechanism 21.1 User-supplied PLI applications 21.1.1 The sizetf class of PLI applications 21.1.2 The checktf class of PLI applications
389	21.1.3 The calltf class of PLI applications 21.1.4 The misctf class of PLI applications 21.1.5 The consumer class of PLI applications 21.2 Associating PLI applications to a class and system task/function name
390	21.3 PLI application arguments 21.3.1 The data C argument 21.3.2 The reason C argument
391	21.3.3 The paramvc C argument
392	22. Using ACC routines 22.1 ACC routine definition 22.2 The handle data type
393	22.3 Using ACC routines 22.3.1 Header files 22.3.2 Initializing ACC routines 22.3.3 Exiting ACC routines 22.4 List of ACC routines by major category
394	22.4.1 Fetch routines
395	22.4.2 Handle routines
396	22.4.3 Next routines
398	22.4.4 Modify routines 22.4.5 Miscellaneous routines
399	22.4.6 VCL routines 22.5 Accessible objects
401	22.5.1 ACC routines that operate on module instances 22.5.2 ACC routines that operate on module ports
402	22.5.3 ACC routines that operate on bits of a port 22.5.4 ACC routines that operate on module paths or data paths
403	22.5.5 ACC routines that operate on intermodule paths 22.5.6 ACC routines that operate on top-level modules 22.5.7 ACC routines that operate on primitive instances
404	22.5.8 ACC routines that operate on primitive terminals 22.5.9 ACC routines that operate on nets
405	22.5.10 ACC routines that operate on reg types 22.5.11 ACC routines that operate on integer, real, and time variables 22.5.12 ACC routines that operate on named events
406	22.5.13 ACC routines that operate on parameters and specparams 22.5.14 ACC routines that operate on timing checks 22.5.15 ACC routines that operate on timing check terminals
407	22.5.16 ACC routines that operate on user-defined system task/function arguments 22.6 ACC routine types and fulltypes
410	22.7 Error handling
411	22.7.1 Suppressing error messages 22.7.2 Enabling warnings 22.7.3 Testing for errors 22.7.4 Example
412	22.7.5 Exception values 22.8 Reading and writing delay values
413	22.8.1 Number of delays for Verilog HDL objects 22.8.2 ACC routine configuration
414	22.8.3 Determining the number of arguments for ACC delay routines 22.8.3.1 Single delay value mode
415	22.8.3.2 Min:typ:max delay value mode
417	22.8.3.3 Calculating turn-off delays from rise and fall delays
418	22.9 String handling 22.9.1 ACC routines share an internal string buffer
419	22.9.2 String buffer reset 22.9.2.1 The buffer reset warning
420	22.9.3 Preserving string values 22.9.4 Example of preserving string values 22.10 Using VCL ACC routines
421	22.10.1 VCL objects 22.10.2 The VCL record definition
424	22.10.3 Effects of acc_initialize() and acc_close() on VCL consumer routines 22.10.4 An example of using VCL ACC routines
427	23. ACC routine definitions
428	23.1 acc_append_delays()
432	23.2 acc_append_pulsere()
434	23.3 acc_close()
435	23.4 acc_collect()
437	23.5 acc_compare_handles()
438	23.6 acc_configure()
447	23.7 acc_count()
448	23.8 acc_fetch_argc()
449	23.9 acc_fetch_argv()
451	23.10 acc_fetch_attribute()
455	23.11 acc_fetch_attribute_int()
456	23.12 acc_fetch_attribute_str()
457	23.13 acc_fetch_defname()
458	23.14 acc_fetch_delay_mode()
460	23.15 acc_fetch_delays()
464	23.16 acc_fetch_direction()
465	23.17 acc_fetch_edge()
467	23.18 acc_fetch_fullname()
469	23.19 acc_fetch_fulltype()
472	23.20 acc_fetch_index()
474	23.21 acc_fetch_location()
476	23.22 acc_fetch_name()
478	23.23 acc_fetch_paramtype()
479	23.24 acc_fetch_paramval()
481	23.25 acc_fetch_polarity()
482	23.26 acc_fetch_precision()
483	23.27 acc_fetch_pulsere()
486	23.28 acc_fetch_range()
487	23.29 acc_fetch_size()
488	23.30 acc_fetch_tfarg(), acc_fetch_itfarg()
490	23.31 acc_fetch_tfarg_int(), acc_fetch_itfarg_int()
491	23.32 acc_fetch_tfarg_str(), acc_fetch_itfarg_str()
492	23.33 acc_fetch_timescale_info()
494	23.34 acc_fetch_type()
496	23.35 acc_fetch_type_str()
497	23.36 acc_fetch_value()
502	23.37 acc_free()
503	23.38 acc_handle_by_name()
505	23.39 acc_handle_calling_mod_m
506	23.40 acc_handle_condition()
507	23.41 acc_handle_conn()
508	23.42 acc_handle_datapath()
509	23.43 acc_handle_hiconn()
511	23.44 acc_handle_interactive_scope()
512	23.45 acc_handle_loconn()
513	23.46 acc_handle_modpath()
515	23.47 acc_handle_notifier()
516	23.48 acc_handle_object()
518	23.49 acc_handle_parent()
519	23.50 acc_handle_path()
520	23.51 acc_handle_pathin()
521	23.52 acc_handle_pathout()
522	23.53 acc_handle_port()
524	23.54 acc_handle_scope()
525	23.55 acc_handle_simulated_net()
527	23.56 acc_handle_tchk()
531	23.57 acc_handle_tchkarg1()
533	23.58 acc_handle_tchkarg2()
534	23.59 acc_handle_terminal()
535	23.60 acc_handle_tfarg(), acc_handle_itfarg()
537	23.61 acc_handle_tfinst()
538	23.62 acc_initialize()
539	23.63 acc_next()
543	23.64 acc_next_bit()
545	23.65 acc_next_cell()
546	23.66 acc_next_cell_load()
548	23.67 acc_next_child()
549	23.68 acc_next_driver()
550	23.69 acc_next_hiconn()
552	23.70 acc_next_input()
554	23.71 acc_next_load()
556	23.72 acc_next_loconn()
557	23.73 acc_next_modpath()
558	23.74 acc_next_net()
559	23.75 acc_next_output()
561	23.76 acc_next_parameter()
562	23.77 acc_next_port()
564	23.78 acc_next_portout()
565	23.79 acc_next_primitive()
566	23.80 acc_next_scope()
567	23.81 acc_next_specparam()
568	23.82 acc_next_tchk()
570	23.83 acc_next_terminal()
571	23.84 acc_next_topmod()
572	23.85 acc_object_in_typelist()
574	23.86 acc_object_of_type()
576	23.87 acc_product_type()
578	23.88 acc_product_version()
579	23.89 acc_release_object()
580	23.90 acc_replace_delays()
584	23.91 acc_replace_pulsere()
587	23.92 acc_reset_buffer()
588	23.93 acc_set_interactive_scope()
589	23.94 acc_set_pulsere()
591	23.95 acc_set_scope()
593	23.96 acc_set_value()
598	23.97 acc_vcl_add()
600	23.98 acc_vcl_delete()
601	23.99 acc_version()
602	24. Using TF routines 24.1 TF routine definition 24.2 TF routine system task/function arguments 24.3 Reading and writing system task/function argument values 24.3.1 Reading and writing 2-state parameter argument values 24.3.2 Reading and writing 4-state values
603	24.3.3 Reading and writing strength values 24.3.4 Reading and writing to memories 24.3.5 Reading and writing string values 24.3.6 Writing return values of user-defined functions 24.3.7 Writing the correct C data types
604	24.4 Value change detection 24.5 Simulation time 24.6 Simulation synchronization
605	24.7 Instances of user-defined tasks or functions 24.8 Module and scope instance names 24.9 Saving information from one system TF call to the next 24.10 Displaying output messages 24.11 Stopping and finishing
606	25. TF routine definitions
607	25.1 io_mcdprintf()
608	25.2 io_printf()
609	25.3 mc_scan_plusargs()
610	25.4 tf_add_long()
611	25.5 tf_asynchoff(), tf_iasynchoff()
612	25.6 tf_asynchon(), tf_iasynchon()
613	25.7 tf_clearalldelays(), tf_iclearalldelays()
614	25.8 tf_compare_long()
615	25.9 tf_copypvc_flag(), tf_icopypvc_flag()
616	25.10 tf_divide_long()
617	25.11 tf_dofinish()
618	25.12 tf_dostop()
619	25.13 tf_error()
620	25.14 tf_evaluatep(), tf_ievaluatep()
621	25.15 tf_exprinfo(), tf_iexprinfo()
624	25.16 tf_getcstringp(), tf_igetcstringp()
625	25.17 tf_getinstance()
626	25.18 tf_getlongp(), tf_igetlongp()
627	25.19 tf_getlongtime(), tf_igetlongtime()
628	25.20 tf_getnextlongtime()
629	25.21 tf_getp(), tf_igetp()
630	25.22 tf_getpchange(), tf_igetpchange()
631	25.23 tf_getrealp(), tf_igetrealp()
632	25.24 tf_getrealtime(), tf_igetrealtime()
633	25.25 tf_gettime(), tf_igettime()
634	25.26 tf_gettimeprecision(), tf_igettimeprecision()
635	25.27 tf_gettimeunit(), tf_igettimeunit()
636	25.28 tf_getworkarea(), tf_igetworkarea()
637	25.29 tf_long_to_real()
638	25.30 tf_longtime_tostr()
639	25.31 tf_message()
641	25.32 tf_mipname(), tf_imipname()
642	25.33 tf_movepvc_flag(), tf_imovepvc_flag()
643	25.34 tf_multiply_long()
644	25.35 tf_nodeinfo(), tf_inodeinfo()
648	25.36 tf_nump(), tf_inump()
649	25.37 tf_propagatep(), tf_ipropagatep()
650	25.38 tf_putlongp(), tf_iputlongp()
651	25.39 tf_putp(), tf_iputp()
652	25.40 tf_putrealp(), tf_iputrealp()
653	25.41 tf_read_restart()
654	25.42 tf_real_to_long()
655	25.43 tf_rosynchronize(), tf_irosynchronize()
656	25.44 tf_scale_longdelay()
657	25.45 tf_scale_realdelay()
658	25.46 tf_setdelay(), tf_isetdelay()
659	25.47 tf_setlongdelay(), tf_isetlongdelay()
660	25.48 tf_setrealdelay(), tf_isetrealdelay()
661	25.49 tf_setworkarea(), tf_isetworkarea()
662	25.50 tf_sizep(), tf_isizep()
663	25.51 tf_spname(), tf_ispname()
664	25.52 tf_strdelputp(), tf_istrdelputp()
666	25.53 tf_strgetp(), tf_istrgetp()
667	25.54 tf_strgettime()
668	25.55 tf_strlongdelputp(), tf_istrlongdelputp()
670	25.56 tf_strrealdelputp(), tf_istrrealdelputp()
672	25.57 tf_subtract_long()
674	25.58 tf_synchronize(), tf_isynchronize()
675	25.59 tf_testpvc_flag(), tf_itestpvc_flag()
676	25.60 tf_text()
677	25.61 tf_typep(), tf_itypep()
678	25.62 tf_unscale_longdelay()
679	25.63 tf_unscale_realdelay()
680	25.64 tf_warning()
681	25.65 tf_write_save()
682	26. Using VPI routines 26.1 VPI system tasks and functions 26.2 The VPI interface 26.2.1 VPI callbacks
683	26.2.2 VPI access to Verilog HDL objects and simulation objects 26.2.3 Error handling 26.2.4 Function availability 26.2.5 Traversing expressions
684	26.3 VPI object classifications
685	26.3.1 Accessing object relationships and properties
686	26.3.2 Object type properties 26.3.3 Object file and line properties
687	26.3.4 Delays and values 26.4 List of VPI routines by functional category
689	26.5 Key to data model diagrams
690	26.5.1 Diagram key for objects and classes 26.5.2 Diagram key for accessing properties
691	26.5.3 Diagram key for traversing relationships
692	26.6 Object data model diagrams
693	26.6.1 Module
694	26.6.2 Instance arrays
695	26.6.3 Scope 26.6.4 IO declaration
696	26.6.5 Ports
697	26.6.6 Nets and net arrays
699	26.6.7 Regs and reg arrays
701	26.6.8 Variables
702	26.6.9 Memory
703	26.6.10 Object range 26.6.11 Named event
704	26.6.12 Parameter, specparam
705	26.6.13 Primitive, prim term
706	26.6.14 UDP
707	26.6.15 Module path, path term 26.6.16 Intermodule path
708	26.6.17 Timing check 26.6.18 Task, function declaration
709	26.6.19 Task and function call
710	26.6.20 Frames
711	26.6.21 Delay terminals 26.6.22 Net drivers and loads 26.6.23 Reg drivers and loads
712	26.6.24 Continuous assignment
713	26.6.25 Simple expressions
714	26.6.26 Expressions
715	26.6.27 Process, block, statement, event statement
716	26.6.28 Assignment 26.6.29 Delay control 26.6.30 Event control 26.6.31 Repeat control
717	26.6.32 While, repeat, wait 26.6.33 For 26.6.34 Forever
718	26.6.35 If, if-else 26.6.36 Case
719	26.6.37 Assign statement, deassign, force, release 26.6.38 Disable
720	26.6.39 Callback 26.6.40 Time queue 26.6.41 Active time format
721	26.6.42 Attributes
722	26.6.43 Iterator
723	27. VPI routine definitions
724	27.1 vpi_chk_error()
725	27.2 vpi_compare_objects()
726	27.3 vpi_control()
727	27.4 vpi_flush()
728	27.5 vpi_free_object()
729	27.6 vpi_get()
730	27.7 vpi_get_cb_info()
731	27.8 vpi_get_data()
733	27.9 vpi_get_delays()
736	27.10 vpi_get_str()
737	27.11 vpi_get_systf_info()
738	27.12 vpi_get_time()
739	27.13 vpi_get_userdata()
740	27.14 vpi_get_value()
746	27.15 vpi_get_vlog_info()
747	27.16 vpi_handle()
748	27.17 vpi_handle_by_index()
749	27.18 vpi_handle_by_multi_index()
750	27.19 vpi_handle_by_name()
751	27.20 vpi_handle_multi()
752	27.21 vpi_iterate()
753	27.22 vpi_mcd_close()
754	27.23 vpi_mcd_flush()
755	27.24 vpi_mcd_name()
756	27.25 vpi_mcd_open()
757	27.26 vpi_mcd_printf()
758	27.27 vpi_mcd_vprintf()
759	27.28 vpi_printf()
760	27.29 vpi_put_data()
762	27.30 vpi_put_delays()
765	27.31 vpi_put_userdata()
766	27.32 vpi_put_value()
769	27.33 vpi_register_cb()
770	27.33.1 Simulation-event-related callbacks
772	27.33.1.1 Callbacks on Individual Statements 27.33.1.2 Behavior by Statement Type
773	27.33.1.3 Registering Callbacks on a Module-wide Basis 27.33.2 Simulation-time-related callbacks
774	27.33.3 Simulator action and feature related callbacks
777	27.34 vpi_register_systf()
778	27.34.1 System task and function callbacks
779	27.34.2 Initializing VPI system task/function callbacks
780	27.34.3 Registering multiple system tasks and functions
781	27.35 vpi_remove_cb()
782	27.36 vpi_scan()
783	27.37 vpi_vprintf()
784	Annex A Formal syntax definition A.1 Source text A.1.1 Library source text A.1.2 Configuration source text
785	A.1.3 Module and primitive source text A.1.4 Module parameters and ports A.1.5 Module items
786	A.2 Declarations A.2.1 Declaration types A.2.1.1 Module parameter declarations
787	A.2.1.2 Port declarations A.2.1.3 Type declarations
788	A.2.2 Declaration data types A.2.2.1 Net and variable types A.2.2.2 Strengths A.2.2.3 Delays A.2.3 Declaration lists
789	A.2.4 Declaration assignments A.2.5 Declaration ranges A.2.6 Function declarations A.2.7 Task declarations
790	A.2.8 Block item declarations
791	A.3 Primitive instances A.3.1 Primitive instantiation and instances A.3.2 Primitive strengths
792	A.3.3 Primitive terminals A.3.4 Primitive gate and switch types A.4 Module and generated instantiation A.4.1 Module instantiation A.4.2 Generated instantiation
793	A.5 UDP declaration and instantiation A.5.1 UDP declaration A.5.2 UDP ports
794	A.5.3 UDP body A.5.4 UDP instantiation A.6 Behavioral statements A.6.1 Continuous assignment statements A.6.2 Procedural blocks and assignments
795	A.6.3 Parallel and sequential blocks A.6.4 Statements A.6.5 Timing control statements
796	A.6.6 Conditional statements
797	A.6.7 Case statements A.6.8 Looping statements A.6.9 Task enable statements A.7 Specify section A.7.1 Specify block declaration
798	A.7.2 Specify path declarations A.7.3 Specify block terminals A.7.4 Specify path delays
800	A.7.5 System timing checks A.7.5.1 System timing check commands
801	A.7.5.2 System timing check command arguments A.7.5.3 System timing check event definitions
802	A.8 Expressions A.8.1 Concatenations A.8.2 Function calls
803	A.8.3 Expressions
804	A.8.4 Primaries A.8.5 Expression left-side values
805	A.8.6 Operators A.8.7 Numbers
806	A.8.8 Strings A.9 General A.9.1 Attributes A.9.2 Comments A.9.3 Identifiers
807	A.9.4 Identifier branches
808	A.9.5 White space
809	Annex B List of keywords
811	Annex C System tasks and functions C.1 $countdrivers
812	C.2 $getpattern
813	C.3 $input C.4 $key and $nokey
814	C.5 $list C.6 $log and $nolog C.7 $reset, $reset_count, and $reset_value
815	C.8 $save, $restart, and $incsave
816	C.9 $scale C.10 $scope C.11 $showscopes
817	C.12 $showvars C.13 $sreadmemb and $sreadmemh
818	Annex D Compiler directives D.1 `default_decay_time D.2 `default_trireg_strength
819	D.3 `delay_mode_distributed D.4 `delay_mode_path D.5 `delay_mode_unit D.6 `delay_mode_zero
820	Annex E acc_user.h
829	Annex F veriuser.h
837	Annex G vpi_user.h
851	Annex H Bibliography
852	Index Symbols
855	Numerics A
859	B C
861	D E
862	F
863	G H
864	I K L
865	M
866	N
867	O
868	P
869	Q
870	R
871	S
873	T
876	U V
878	W
879	X Z