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BSI PD IEC/TS 62878-2-3:2015

BSI PD IEC/TS 62878-2-3:2015

$142.49

Device embedded substrate – Guidelines. Design guide

Published By Publication Date Number of Pages
BSI 2015 28
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This part of IEC 62878 describes the design guide of device embedded substrates.

The design guide of device embedded substrate is essentially the same as that of various electronic circuit boards. This part of IEC 62878 enables a thorough understanding of circuit design, structure design, board design, board manufacturing, jisso (assembly processes) and tests of products.

This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.

The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421.

PDF Catalog

PDF Pages PDF Title
4 English
CONTENTS
6 FOREWORD
8 INTRODUCTION
9 1 Scope
2 Normative references
3 Terms, definition and abbreviations
3.1 Terms and definitions
3.2 Abbreviations
10 4 Structure of device embedded substrates
4.1 General
4.2 Specification of the top and bottom surfaces of a device embedded substrate
Figures
Figure 1 – Definition of top and bottom surfaces of a device embedded substrate
11 4.3 Definition of layers of a device embedded substrate
Figure 2 – Definition of top and bottom surfaces for mounting on a mother board
Figure 3 – Names of layers in pad connection
12 Figure 4 – Additional information concerning the interconnection position
13 Figure 5 – Names of layers in via connection [I]
Figure 6 – Names of layers in via connection [II]
14 4.4 Conductor spacing at a terminal
Figure 7 – Names of layers in via connection [III]
Tables
Table 1 – Name of layers of device embedded board
15 Figure 8 – Definitions of dielectric gap and layer gap in the pad connection method
Figure 9 – Definitions of dielectric gap and layer gap in the via connection method
16 Figure 10 – Additional illustration of dielectric gap
Figure 11 – Additional illustration of layer gap
17 5 Conditions to prepare base and embedding devices
5.1 Conditions for base
Table 2 – Recommendation for device assembly to base substrate for device embedded boards
18 5.2 Conditions for embedding devices
Table 3 – Embedding recommendation
19 Table 4 – Mounting methods of semiconductor devices
20 6 Recommendation for embedding devices
Table 5 – Embedding device
21 7 Design specification of device embedded substrate
7.1 General
7.2 Items to be included in the design specification
7.2.1 Graphical indication of device embedding substrate
Figure 12 – Additional drawing
22 7.2.2 Design specification template
Figure 13 – Forbidden wiring area
23 Table 6 – Specification of device embedded substrate 1
24 Table 7 – Specification of device embedded substrate 2
25 Table 8 – Specification of device embedded substrate 3
26 Bibliography

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BSI PD IEC/TS 62878-2-3:2015
$142.49