BS EN 60749-26:2014
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Semiconductor devices. Mechanical and climatic test methods – Electrostatic discharge (ESD) sensitivity testing. Human body model (HBM)
Published By | Publication Date | Number of Pages |
BSI | 2014 | 44 |
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD).
The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels.
ESD testing of semiconductor devices is selected from this test method, the machine model (MM) test method (see IEC 60749-27) or other ESD test methods in the IEC 60749 series. The HBM and MM test methods produce similar but not identical results; unless otherwise specified, this test method is the one selected.
PDF Catalog
PDF Pages | PDF Title |
---|---|
6 | English CONTENTS |
8 | 1 Scope 2 Normative references 3 Terms and definitions |
11 | 4 Apparatus and required equipment 4.1 Waveform verification equipment |
12 | 4.2 Oscilloscope 4.3 Additional requirements for digital oscilloscopes 4.4 Current transducer (inductive current probe) 4.5 Evaluation loads 4.6 Human body model simulator |
13 | 4.7 HBM test equipment parasitic properties 5 Stress test equipment qualification and routine verification 5.1 Overview of required HBM tester evaluations 5.2 Measurement procedures 5.2.1 Reference pin pair determination Figures Figure 1 – Simplified HBM simulator circuit with loads |
14 | 5.2.2 Waveform capture with current probe 5.2.3 Determination of waveform parameters |
15 | Figure 2 – Current waveform through shorting wires |
16 | Figure 3 – Current waveform through a 500 Ω resistor |
17 | 5.2.4 High voltage discharge path test 5.3 HBM tester qualification 5.3.1 HBM ESD tester qualification requirements 5.3.2 HBM tester qualification procedure Figure 4 – Peak current short circuit ringing waveform |
18 | 5.4 Test fixture board qualification for socketed testers |
19 | 5.5 Routine waveform check requirements 5.5.1 Standard routine waveform check description 5.5.2 Waveform check frequency Tables Table 1 – Waveform specification |
20 | 5.5.3 Alternate routine waveform capture procedure 5.6 High voltage discharge path check 5.6.1 Relay testers 5.6.2 Non-relay testers 5.7 Tester waveform records 5.7.1 Tester and test fixture board qualification records 5.7.2 Periodic waveform check records |
21 | 5.8 Safety 5.8.1 Initial set-up 5.8.2 Training 5.8.3 Personnel safety 6 Classification procedure 6.1 Devices for classification 6.2 Parametric and functional testing 6.3 Device stressing |
22 | 6.4 Pin categorization 6.4.1 General 6.4.2 No connect pins 6.4.3 Supply pins |
23 | 6.4.4 Non–supply pins 6.5 Pin groupings 6.5.1 Supply pin groups |
24 | 6.5.2 Shorted non-supply pin groups 6.6 Pin stress combinations 6.6.1 Pin stress combination categorisation |
25 | Table 2 – Preferred pin combinations sets |
26 | 6.6.2 Non-supply and supply to supply combinations (1, 2, … N) Table 3 – Alternative pin combinations sets |
27 | 6.6.3 Non-supply to non-supply combinations |
28 | 6.7 Testing after stressing 7 Failure criteria 8 Component classification Table 4 – HBM ESD component classification levels |
29 | Annex A (informative)HBM test method flow chart |
32 | Annex B (informative)HBM test equipment parasitic properties Figure B.1 – Diagram of trailing pulse measurement setup |
33 | Figure B.2 – Positive stress at 4 000 V Figure B.3 – Negative stress at 4 000 V |
34 | Figure B.4 – Illustration of measuring voltage before HBM pulsewith a Zener diode or a device Figure B.5 – Example of voltage rise before the HBM current pulse across a 9,4 V Zener diode |
36 | Annex C (informative)Example of testing a product using Table 2, Table 3,or Table 2 with a two-pin HBM tester |
37 | Figure C.1 – Example to demonstrate the idea of the partitioned test |
38 | Table C.1 – Product testing in accordance with Table 2 |
39 | Table C.2 – Product testing in accordance with Table 3 |
40 | Table C.3 – Alternative product testing in accordance with Table 2 |
42 | Annex D (informative)Examples of coupled non-supply pin pairs |